Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2000-07-21
2001-10-02
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S022000, C710S023000, C710S028000, C710S029000
Reexamination Certificate
active
06298397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer control method, a data transfer control system, and an information recording medium in an information processing apparatus having a computer arrangement in which DMA controllers are connected to a common bus and data transfer is performed.
2. Description of the Related Art
Generally speaking, in an information processing apparatus, for a purpose of transmission and reception of data with a peripheral device, a DMA controller (hereinafter, simply referred to as a ‘DMAC’) is connected to a system bus or an I/O bus, and, by using the DMAC, DMA (Direct Memory Access) is performed, that is, a memory is directly accessed.
In many cases, data transfer performed with a peripheral device is performed in an asynchronous method, and data transfer is performed with handshaking. In such a case, a capacity of a bus used for data transfer is not previously known clearly.
Further, when data transfer is performed synchronously with a peripheral device or a network, a capacity of a bus used when the synchronous data transfer is performed, a maximum capacity of the bus used when data transfer is performed, and, also, a capacity of the bus used when a transaction is performed by a CPU are considered. Thus, a specification of the bus is determined, and, the bus is designed, or the bus is obtained, as a result of selection. Thereby, it is guaranteed that the entire transaction is performed without stagnation.
However, thereby, the specification of the bus is excessive except for a rare case where congestion of the bus occurs.
Further, in an expansion I/
0
, it is not determined at a timing of designing a system as to which expansion board is to be inserted and what amount of data transfer is required. Thereby, unexpected congestion occurs in a bus when the system is actually used, and data transfer may not be performed without stagnation.
In particular, in data transfer control in an information processing apparatus in the related art, a capacity of a bus used when a DMAC, a CPU, and so forth use the bus, and a capacity of the bus used when data transfer is performed by a peripheral device are not considered. As a result, a new DMA is started when new data transfer is requested from an application program or the like even in a condition where the bus is already saturated. When such a situation occurs, loss of data occurs in an interface which performs synchronous data transfer using a certain capacity of the bus. Thus, a serious situation may occur in the system. Such a problem may occur not only in an interface using the newly started DMA but also in every interface which performs synchronous data transfer.
For example, when data transfer in a new interface performed by an application program or the like is required under a condition where data transfer in an interface, which needs data transfer of a fixed data transfer rate, such as a video interface, a network interface or the like, has already been performed by using a common bus, a new DMA is started even in a case where there is no sufficient free capacity of the bus. As a result, the data transfer is not guaranteed. Such a problem may occur in particular in a case where successive data transfer such as that of an operation for copying a large amount of data or data transfer by a periodically performed program is required.
Further, for example, in a case of using an IEEE 1394, in which data of frequencies of 100 MHz, 200 MHz and 400 MHz are mixed in one interface, a data transfer rate of data reception is not known until data from the interface is actually received, and, thus, a capacity of a bus needed for DMA used for storing the data in a memory cannot be previously known. As a result, the data may not be completely stored in the memory.
In an interface for asynchronous data transfer, because data transmission and reception is performed with handshaking, a data transfer rate depends on a particular device with which communication is performed, and, thus, a capacity of bus needed for DMA used for storing data in a memory cannot be previously known. As a result, data may not be completely stored in the memory for a particular device with which communication is performed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data transfer control method, a data transfer control system and an information recording medium, in which data transfer of a necessary data transfer rate can be guaranteed for each of a plurality of DMACs each of which needs a predetermined data transfer rate and is connected to a common bus.
In a data transfer control, according to the present invention, for controlling direct memory access performed by direct memory access controllers in a system including processors, the direct memory access controllers being connected with a common bus,
it is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration;
the newly requested direct memory access is started when it is determined that the direct memory access can be started;
starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started; and
the newly requested direct memory access, which has been kept waiting, is started, when any direct memory access which has already been carried out finishes, and enough capacity is free in the common bus for carrying out the newly requested direct memory access.
Thus, when data transfer for an interface is newly requested by an application program, a system control program or the like, and starting of newly requested DMA for the interface is requested, and when the newly requested DMA for the interface cannot be started in consideration of a free capacity of the common bus, the starting of the newly requested DMA is kept waiting. Thereby, it can be prevented that data transfer cannot be guaranteed due to starting of the newly requested DMA when the data transfer for an interface which needs data transfer of a fixed data transfer rate has been already started using the common bus. Thus, it is possible to guarantee data transfer at a necessary data transfer rate for each of the plurality of DMACs each of which needs the predetermined data transfer rate and is connected with the common bus.
The rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors may be calculated using a data transfer rate needed by the direct memory access performed by each of the direct memory controllers, the size of data which is transferred in one direct memory access operation or the size of data which the memory can accept, the latency for accessing the memory, and the latency for bus-right arbitration.
Thus, the rate of using the bus at the present time which is used for determining whether newly requested starting of DMA can be permitted can be easily calculated based on information concerning DMA which has been already started. As a result, it is not necessary to change the hardware arrangement to incorporate a special circuit for this purpose.
It may be determined whether or not an interface can be activated, the interface being connected with the direct memory access controller and receiving data at an arbitrary timing to the system, using a rate of using the bus calculated by using a data transfer rate needed by direct memory access when data received by the interface is written in the m
Lee Thomas
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Park Ilwoo
Ricoh & Company, Ltd.
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