Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
2006-04-11
2006-04-11
Peyton, Tammara (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S005000, C710S052000, C710S053000, C710S104000, C710S109000
Reexamination Certificate
active
07028109
ABSTRACT:
A plurality of pipe regions PIPE0to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.
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Kubota Shinsuke
Matsuda Kuniaki
Saito Nobuyuki
Shimono Hiroaki
Oliff & Berridg,e PLC
Peyton Tammara
Seiko Epson Corporation
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