Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-07-11
2006-07-11
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
Reexamination Certificate
active
07076626
ABSTRACT:
A data transfer control device includes a DMAC1that writes a packet transferred from a BUS1(IEEE 1394 or USB), to a SRAM, a DMAC2that reads the written isochronous data from the SRAM and writes it to a SDRAM, and a DMAC3that reads the written isochronous data and transfers it to a BUS2side. During transmission, isochronous data is read from the SDRAM and written to SRAM, and an isochronous packet including the written isochronous data is transferred to the BUS1side. The SRAM includes an isochronous data area and an asynchronous data area. The SRAM is provided insides the data transfer control device and the SDRAM is provided on outside the data transfer control device.
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Oka Yoshimi
Saito Nobuyuki
Ellis Kevin L.
Oliff & Berridg,e PLC
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