Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-06-26
2007-06-26
Perveen, Rehana (Department: 2116)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
Reexamination Certificate
active
11264170
ABSTRACT:
A data transfer control device including a buffer is provided which includes an EP2area (a data storage area set to FIFO) and a CSW area (a randomly accessible status storage area), when data and a CSW are allocated as information to be transferred through one end point EP2.When a phase has switched from a USE data phase (data transport) to a status phase (status transport), the information read area is switched from the EP2area to the CSW area. and IN data to be transferred from the end point EP2to a host is read from the CSW area. A CSW0area for success status and a CSW1area for non-success status are provided, and a status block packet in which is set either success or non-success default information is previously written therein.
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Ishida Takuya
Kamihara Yoshiyuki
Chang Eric
Oliff & Berridg,e PLC
Perveen Rehana
Seiko Espon Corporation
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