Data transfer control device and electronic equipment

Details Data transfer control device and electronic equipment Data transfer control device and electronic equipment

2000-10-11

2004-10-26

Fleming, Fritz (Department: 2661)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S052000, C711S206000

Reexamination Certificate

active

06810445

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer control device and electronic equipment comprising the same, and, in particular, to a data transfer control device that enables data transfer in accordance with the IEEE 1394 standard between a plurality of nodes connected to a bus, and electronic equipment comprising the same.
2. Description of Related Art
An interface standard called IEEE 1394 has recently been attracting much attention. This IEEE 1394 has standardized high-speed serial bus interfaces that can handle the next generation of multimedia devices. IEEE 1394 makes it possible to handle data that is required to have real-time capabilities, such as moving images. A bus in accordance with IEEE 1394 can be connected not only to peripheral equipment for computers, such as printers, scanners, CD-RW drives, and hard disk drives, but also to domestic appliances such as video cameras, VTRs, and TVs. This standard is therefore expected to enable a dramatic acceleration of the digitalization of electronic equipment.
However, some technical problems have been identified with such a data transfer control device conforming to IEEE 1394, as described below.
That is to say, the current IEEE 1394 standard does make it possible to implement transfer speeds up to a maximum of 400 Mbps. In practice, however, the presence of overhead processing forces the actual transfer speeds of the entire system to be much slower. In other words, the firmware (processing means) running on a CPU require large amounts of time for processes such as preparing for transmitting data, dividing transfer data into packets, and issuing the transfer start command, which means it is not possible to implement high-speed data transfer overalls no matter how fast the data can be transferred over the buses.
A particular problem lies in the fact that a CPU incorporated into peripheral equipment has a lower processing capability than the CPU incorporated into the host system, such as a personal computer. This makes the problem of overhead processing in the firmware and application software extremely serious. It is therefore desirable to provide techniques that are capable of efficiently solving this overhead problem.
In addition, when data is transferred between an initiator (host) such as a personal computer and a target (device) such as a CD-RW drive or printer, there are restrictions that prohibit data transfers that exceed page boundaries within a data buffer (storage means) on the initiator side. If the initiator has specified addresses by an indirect addressing method using a page table, it is not particularly necessary for the target side to consider such restrictions. If the initiator has specified addresses by a direct addressing method, however, a problem is raised in that the target side has to perform data transfers while observing such restrictions.
SUMMARY OF THE INVENTION
The present invention was devised in the light of the above described technical problems, and has as an objective thereof the provision of a data transfer control device that makes it possible to implement high-speed data transfer while observing the restriction on traversing page boundaries, regardless of the existence
onexistence of a page table, and electronic equipment that uses the same.
In order to solve the above described technical problems, according to a first aspect of the present invention, there is provided a data transfer control device for transferring data among a plurality of nodes that are connected to a bus. The data transfer control device comprises:
a page table fetch circuit that operates when a page table exists in a storage means of another node, to fetch the page table from the other node;
a page table creation circuit that operates when no page table exists in a storage means of the other node, to create a virtual page table based on page boundary information; and
a transfer execution circuit which executes processing to divide transfer data into packets that do not traverse page boundaries, based on the thus fetched or created page table, and transmit the packets.
With this aspect of the invention, if a page table exists in the storage means of the other node, that page table is fetched; if no page table exists in the storage means of the other node, a virtual page table is created. The thus fetched or created page table is then used to divide transfer data into packets that do not traverse page boundaries, for transmission. With this aspect of the invention configured as described above, data can be transferred even if no page table exists, using a created virtual page table, so that the transfer execution processing after the page table has been fetched or created can be made common. In other words, data can be transferred by the same transfer execution processing, regardless of whether or not a page table exists. This simplifies the processing and makes the circuitry more compact. Since data is transmitted by using a virtual page table if no page table exists, this aspect of the invention makes it possible to implement high-speed data transfer while observing the restriction on traversing page boundaries of the storage means of the other node.
When a processing means has issued a transfer start command, the page table fetch circuit may execute processing to automatically fetch a page table or the page table creation circuit may execute processing to automatically create a page table; and the transfer execution circuit may execute processing to automatically divide transfer data equivalent of a page table into a series of packets and transfer the thus-divided series of packets continuously. This ensures that, when the processing means issues a transfer start command, the page table is automatically fetched or created, transfer data equivalent of a page-table is automatically divided into a series of packets, and those packets are transmitted. This therefore enables a huge reduction in the processing load on the processing means such as firmware, enabling a large increase in the actual transfer speed of data.
The data transfer control device may further comprise a payload division circuit for dividing transfer data into packets of a payload size, based on page table element information possessed by a page table. This ensures that the payload division of packets is also done automatically by the hardware, thus making it possible to further reduce the processing load on the processing means such as firmware.
The data transfer control device may further comprise randomly accessible packet storage means having a control information area for storing packet control information and a data area for storing packet data, wherein the data area of the packet storage means is separated into a first data area for storing first data for a first layer and a second data area for storing second data for a second layer that is the object of continuous packet transfer by the transfer execution circuit. This ensures that packet control information (such as headers and footers) is stored in a control information area, first data of the packet (such as data for the transaction layer) is stored in a first data area, and second data of the packet (such as data for the application layer) is stored in a second data area. This configuration makes it possible to read the second data out sequentially from the second data area and transmit it to the second layer. This makes it possible to transfer data even faster.
Note that the first data in accordance with the present invention is preferably command data used by the protocol of the first layer and the second data is preferably data used by the application layer.
When a request packet for starting a transaction is transmitted to another node, instruction information for instructing the processing to be performed when a response packet will be received from the other node may be comprised within transaction identification information in the requests packet; and when the response packet is received from the other node, control informa

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