Data transfer control circuit in system LSI

Details Data transfer control circuit in system LSI Data transfer control circuit in system LSI

2006-03-21

2006-03-21

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S003000, C710S306000, C710S052000, C711S158000

Reexamination Certificate

active

07017000

ABSTRACT:
Two bus masters share an external device. One particular bus master has an arrangement for issuing a data pre-read instruction, at the time of issuing a data read request. Upon reception of the data read request accompanying with the data pre-read instruction issued by the particular bus master, an external device controller instructs an external address generator to continuously generate an address for performing normal readout this time, and an address for the next pre-read, and executes readout by the next pre-read address, provided that when the normal readout this time is finished, the bus master has not issued a data read request. The normal data read based on the normal readout address this time is held in a data holder, and the pre-read data read based on the next pre-read address is stored in a pre-read data storage.

REFERENCES:
patent: 5007011 (1991-04-01), Murayama
patent: 6298424 (2001-10-01), Lewchuk et al.
patent: 6880046 (2005-04-01), Yokoi et al.
patent: 6892262 (2005-05-01), Taki
patent: 7-210454 (1995-08-01), None
patent: 2001-229074 (2001-08-01), None

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