Data transfer circuitry, DSP wrapper circuitry and improved proc

Details Data transfer circuitry, DSP wrapper circuitry and improved proc Data transfer circuitry, DSP wrapper circuitry and improved proc

1997-04-04

2000-08-15

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Address formation

Incrementing, decrementing, or shifting circuitry

710129, G06F 1200

Patent

active

061051195

ABSTRACT:
An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.

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