Data transfer circuit and data processing method using data...

Details Data transfer circuit and data processing method using data... Data transfer circuit and data processing method using data...

1999-08-25

2003-01-21

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

Source or destination identifier

C710S267000, C710S262000

Reexamination Certificate

active

06510480

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a register access circuit used in a microcomputer or the like, and a data processing method in the register access circuit when an interruption request signal is output from an interruption request circuit connected to the register access circuit to a central processing unit.
BACKGROUND OF THE INVENTION
For example, a microcomputer used in a system having a construction as shown in
FIG. 7
is composed of a large-scale integrated circuit (hereinafter referred to as an LSI) and a central processing unit (hereinafter referred to as a CPU), and the CPU can access a register inside the LSI via an interface circuit which satisfies a predetermined specification. Further, the CPU is connected to an interruption request circuit from the LSI, although it is not shown in the figure.
First of all, the CPU access to the register will be briefly described. The CPU outputs address information and a write enable signal or a read enable signal to the LSI to request access to the register inside the LSI. Then, the LSI outputs data to the CPU according to the input address information and the write enable signal or the read enable signal. Alternatively, the LSI captures data in the register so that the CPU can read or write the contents of the register inside the LSI.
Next, the operation of the interruption request circuit will be briefly described. The interruption request circuit receives the internal status of the LSI (e.g., end of data processing, generation of an error, a request to the CPU, etc.) as an interruption request signal, from each of circuit blocks inside the LSI. Then, the interruption request circuit appropriately outputs the received interruption request signal to the CPU. In this way, the CPU can know the internal status of the LSI by processing the interruption request signal.
On receipt of the interruption request, the CPU interrupts the processing in progress (main routine) to handle the interruption request. Next, the CPU accesses data decoded in a predetermined address to recognize the cause of the interruption. After recognizing the cause of the interruption, the CPU performs a predetermined process on the LSI. When this process has ended, the CPU clears the interruption cause and returns to the main routine.
However, in the LSI connected to the CPU, there exists a block performing data processing independently of the operation of the CPU. When an error or the like occurs in the data processing performed in this block, this block sometimes outputs an interruption request signal to the CPU independently of the CPU's operation to detect the states of flip-flops.
For example, it is assumed that the instruction word length of the CPU is not equal to the width of an internal bus line of the LSI connected to the CPU, like that the instruction word length of the CPU is 16 bits while the bus width is 32 bits. In this case, when the CPU writes only 16 bits of data in the LSI, if an interruption request signal is output to the CPU from a block performing data processing independently of the operation of the CPU, the CPU performs interruption processing on the LSI. At this time, writing of data to the register has not yet ended because the LSI does not output a write enable signal to the register until 32 bits of data are written in it. That is, register access is undesirably performed although only 16 bits of data are written in the LSI. As the result, the 16 bits of data which have already been written in the LSI are overwritten, and the 16 bits of data are erased.
In this way, even while the CPU accesses the register of the LSI with the result of the CPU's detecting the flip-flop states being “no interruption request”, there is a possibility that a block having no relation with the operation of the CPU outputs an interruption request signal to the CPU and, in this case, there occurs a problem that the data which are being written in the LSI are erased.
The above-described problem has conventionally been solved by adopting the following methods: a method of making the bus width of the LSI equal to the instruction word length of the CPU, such as using an LSI whose internal bus width is equal to the instruction word length of the CPU; a method of employing an internal bus width changing switch, such as providing the LSI with an internal bus width changing switch for changing the internal bus width of the-LSI according to a variety of instruction word lengths of the CPU; and a method of dealing with the problem at the software end of the CPU, such as providing the CPU with software which gives priority to the main routine of the CPU even when an interrupt request signal is generated and does not perform interruption processing until this main routine is ended.
However, in the method of making the bus width of the LSI equal to the instruction word length of the CPU, it is necessary to change the CPU according to every LSI to be connected and, therefore, the software properties in the past cannot be effectively utilized. Hence, this method is not sufficient to solve the above-mentioned problem.
Further, the method of employing an internal bus width changing switch has the following drawback. Although an ordinary LSI is designed so as to have a wide internal bus width to increase the data transfer rate, if the internal bus width of the LSI is changed according to every instruction word length of the CPU, it is difficult to keep the data transfer at a high rate, resulting in degraded performance of hardware. Further, a circuit block for changing the internal bus width is required, whereby the circuit becomes redundant and, further, the circuit scale increases. Therefore, this method is not sufficient to solve the above-mentioned problem.
In the method of dealing with the problem at the software end of the CPU, the data processing rate is determined by a part of the software where the rate is lowest, and this interferes with parallel processing between the software and the hardware, resulting in difficulty in realizing versatile software. Therefore, this method is not sufficient to solve the problem.
Furthermore, there is a method of continuously making access adapted to the internal bus width of the LSI to avoid the above-mentioned problem. In this method, however, with respect to an interruption request which is input asynchronously, the CPU's recognition of the interruption and the processing thereof are determined not by the instruction word length of the CPU but by the internal bus width of the LSI and, therefore, overhead up to the interruption processing occurs, whereby the interruption processing to the hardware is delayed.
This problem will be described in more detail by using FIGS.
6
(
a
) and
6
(
b
) for explaining overhead of firmware. Although firmware as shown in FIG.
6
(
b
) is originally desired, actually recognition of interruption delays by a period of overhead as shown in FIG.
6
(
a
). So, when an interruption is generated, the hardware which has outputted the instruction of interruption is in the stopped state until the interruption is recognized, received and processed, and therefore it takes long time until interruption processing is completed. That is, the period during which the hardware is in the stopped state increases, whereby the data transfer rate cannot be increased.
SUMMARY OF THE INVENTION
The present invention is made to solve the above-described problems and has for its object to provide a register access circuit which can maximize the period during which a CPU and an LSI operate in parallel by constructing the register access circuit so that it can rapidly accept and handle interruption processing instructed by hardware, i.e., by reducing the overhead time until the interruption processing, even when the LSI connected to the CPU has a bus width different from the instruction word length of the CPU, and which realizes high-speed data transfer by increasing the data transfer efficiency, without necessity of making the CPU's instruction word length equal to the LSI's bu

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