Data transfer apparatus with large noise margin and reduced powe

Details Data transfer apparatus with large noise margin and reduced powe Data transfer apparatus with large noise margin and reduced powe

1996-08-29

1998-09-29

Nelms, David C.

Static information storage and retrieval

Read/write circuit

365190, 36518911, 365203, 365206, G11C 1604

Patent

active

058154426

ABSTRACT:
In a data transfer apparatus powered by first and second power supply voltages, a data output circuit generates first complementary output signals, a data transfer circuit having a large load capacitance transfers the first complementary output signals to generate second complementary output signals, and an amplifier circuit amplifies the second complementary output signals to generate third complementary output signals. A first transfer gate circuit is connected between the data output circuit and the data transfer circuit. A second transfer gate circuit is connected between the data transfer circuit and the amplifier circuit. The first, second and third complementary output signals are caused to be approximately at an intermediate level between the first and second voltages.

REFERENCES:
patent: 4161040 (1979-07-01), Satoh
patent: 5233558 (1993-08-01), Fujii et al.
Akira Tanabe et al., "A 30-ns 64-Mb DRAM with Built-in Self-Test and Self-Repair Function", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, pp.1525-1533, Nov. 1992.

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