Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-02-01
2005-02-01
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S723000, C711S173000
Reexamination Certificate
active
06851078
ABSTRACT:
A memory device testing apparatus transfers at high speed a fail signal from a failure analysis memory unit100to a memory failure remedy analysis unit200. The failure analysis memory unit100has a data storage memory110and a compact memory120. The data storage memory110is divided into at least two sub address spaces. The divided sub address spaces are assigned to the addresses in the compact memory120. An address generation control unit reads data stored in the compact memory120. An address generation unit132generates a memory address signal143based on a sub address signal141and a detail address signal142. The detail address signal142is incremented by the address generation control unit125. The data in the sub address space storing the fail signal is transferred to the memory failure remedy analysis unit200. If the data read from the compact memory120does not contain failure information, the data stored in the corresponding sub address space is not transferred.
REFERENCES:
patent: 6097206 (2000-08-01), Takano
Advantest Corporation
De'cady Albert
Kerveros James C.
Osha & May L.L.P.
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