Data transfer apparatus, information processing apparatus,...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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C710S306000, C710S311000

Reexamination Certificate

active

07913026

ABSTRACT:
Provided is a data transfer apparatus having a system bus interface20connected to an MC51, a high-speed I/O bus interface connected to a high-speed I/O bus switch54, a history selection controller10that selects part of transmission/reception data transferred between the MC51and high-speed I/O bus switch54, a buffer section11that is connected to the history selection controller10and retains the part of the transmission/reception data selected by the history selection controller10, and a low-speed bus interface that outputs the part of the transmission/reception data retained by the buffer section11to an observation apparatus200.

REFERENCES:
patent: 6560233 (2003-05-01), Hatanaka et al.
patent: 7715433 (2010-05-01), Boren
patent: 2000-293441 (2000-10-01), None

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