Data transfer apparatus and data transfer method

Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing

Reexamination Certificate

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C710S022000

Reexamination Certificate

active

07844754

ABSTRACT:
A data transfer apparatus includes a processor, a main memory, and a DMAC connected to the main memory via a plurality of buses. The DMAC transfers data to the main memory by bypassing the processor, writes flag data “1” indicating completion of the data transfer processing in a completion status storage area of the main memory, and finally outputs an interrupt signal to the processor. In response to the interrupt signal, an interrupt handler refers to the completion status storage area, and when the flag data is written, reads the data in the main memory and erases the flag data in the completion status storage area.

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patent: 5497450 (1996-03-01), Helmbold et al.
patent: 5535348 (1996-07-01), Leach et al.
patent: 5717952 (1998-02-01), Christiansen et al.

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