Data transfer apparatus

Details Data transfer apparatus Data transfer apparatus

2000-12-26

2004-08-24

Perveen, Rehana (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S028000, C710S033000, C710S052000, C710S053000, C710S060000, C711S147000

Reexamination Certificate

active

06782433

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer apparatus for transferring data from a main memory which is coupled to a main bus to a local memory which is coupled to a local bus.
2. Description of the Related Art
FIG. 6
shows the structure of a conventional data transfer apparatus
100
.
The data transfer apparatus
100
transfers data from a main memory
112
to a local memory
156
.
The data transfer apparatus
100
includes a main bus interface
127
, a local bus interface
134
, a DMA top address register
120
, a DMA transfer word number register
121
for storing the number of words to be DMA-transferred, an adder
104
, a subtracter
103
, and a controller
122
.
The main bus interface
127
and the local bus interface
134
are interconnected via an internal data line
151
and an internal address line
152
.
The main bus interface
127
is coupled to a main data bus
113
and a main address bus
150
. The main data bus
113
and the main address bus
150
are both coupled to peripheral devices for the data transfer apparatus
100
, e.g., a CPU
110
, a DMA controller
111
, and a main memory
112
.
The local bus interface
134
is coupled to a local data bus
128
and a local address bus
135
. The local data bus
128
and the local address bus
135
are both coupled to peripheral devices for the data transfer apparatus
100
, e.g., a local memory
156
, via a bus interface
155
.
An internal data processor
161
is further coupled to the local data bus
128
and the local address bus
135
. The data transfer apparatus
100
and the internal data processor
161
are of a unified memory architecture sharing the local memory
156
. The internal data processor
161
may be, for example, a video output processing circuit.
Herein, it is assumed that when transferring one word at a time from the CPU
110
and the DMA controller
111
to the local memory
156
, the internal bus transfer cycle (or “local bus transfer cycle”) may be ½ of the external bus transfer cycle (or “main bus transfer cycle”).
In practice, however, the external bus transfer cycle and the internal bus transfer cycle may be 10 MHz and 100 MHz, respectively. One reason for this is that the clock of an internal bus of a chip is designed for a faster operation than the clock of an external bus of the chip.
In the present specification, any data transfer by the CPU
110
from the main memory
112
to the local memory
156
will be referred to as a “CPU transfer”. Any data transfer by the DMA controller
111
from the main memory
112
to the local memory
156
will be referred to as a “DMA transfer”.
The operation of the CPU
110
, the DMA controller
111
, and the data transfer apparatus
100
will be summarized below.
The main memory
112
and the local memory
156
are memory-mapped to the CPU
110
and the DMA controller
111
.
The CPU
110
and the DMA controller
111
, which alternately or consecutively acquire the right to use the main data bus
113
, transfer data via the data transfer apparatus
100
.
(CPU Transfer)
Once acquiring the right to use the main data bus
113
, the CPU
110
reads data from the main memory
112
(as a “transfer source”) via the main data bus
113
and the main address bus
150
. The CPU
110
asserts a CPU access control signal
123
which is output to the data transfer apparatus
100
, and outputs the data which has been read from the main memory
112
to the data transfer apparatus
100
(as a “transfer destination”) via the main data bus
113
and the main address bus
150
.
(DMA Transfer)
In the case of a DMA transfer, it is necessary to utilize the CPU
110
to establish initial settings for DMA transfer in the DMA controller
111
and the data transfer apparatus
100
.
First, a top address of the main memory
112
(which is the transfer source) and the number of words to be transferred are set in an internal register (not shown) of the DMA controller
111
, and a request is made to begin a DMA transfer.
Next, through a CPU access, the CPU
110
sets a top address of the local memory
156
(which is the transfer destination) for DMA transfer, the top address being set in the DMA top address register
120
in the data transfer apparatus
100
.
Next, through a CPU access, the CPU
110
sets the number of DMA transfers to be made in the DMA transfer word number register
121
in the data transfer apparatus
100
.
As soon as the initial settings for DMA transfer are complete and the data transfer apparatus
100
becomes ready for data transfer to the local memory
156
, the data transfer apparatus
100
asserts a DMA request signal
126
.
Upon detecting the assertion of the DMA request signal
126
and acquiring the right to use the main data bus
113
, the DMA controller
111
reads data from the main memory
112
(as a “transfer source”) via the main data bus
113
and the main address bus
150
. The DMA controller
111
asserts a DMA access control signal
125
which is output to the data transfer apparatus
100
, and outputs the data which has been read from the main memory
112
to the data transfer apparatus
100
(as a “transfer destination”) via the main data bus
113
.
During a DMA transfer, no address for the local memory
156
is output to the data transfer apparatus
100
as a transfer destination.
Next, the operations of the data transfer apparatus
100
and the bus controller
133
will be summarized below.
When performing a CPU transfer or a DMA transfer, the data transfer apparatus
100
outputs a local bus request signal
130
to the bus controller
133
for requesting a right to use the local data bus
128
and the local address bus
135
, to which the local memory
156
(which is the data transfer destination) is coupled. Herein, it is assumed that the local data bus
128
and the local address bus
135
are shared by a plurality of processing blocks. In the case where a local bus request signal
160
has not been issued from the internal data processor
161
, the bus controller
133
outputs a local bus grant signal
129
to the data transfer apparatus
100
.
Next, the internal operation of the data transfer apparatus
100
will be described.
(CPU Transfer)
Data and a local memory address which are output from the CPU
110
along with the CPU access control signal
123
are temporarily stored in the main bus interface
127
.
Upon receiving the CPU access control signal
123
from the CPU
110
, the controller
122
asserts a wait control signal
124
which is output to the CPU
110
, and outputs the local bus request signal
130
to the bus controller
133
.
Upon receiving the local bus grant signal
129
from the bus controller
133
, the controller
122
outputs a local bus control signal
162
to the local bus interface
134
. In accordance with the local bus control signal
162
, the local bus interface
134
outputs the data on the internal data line
151
to the local data bus
128
, and outputs an address on the internal address line
152
to the local address bus
135
.
The local bus control signal
162
includes a field which indicates the timing with which to output data on the local data bus
128
and an address selection field which indicates whether the address on the internal address line
152
or the address on the DMA address line
153
is to be output to the local address bus
135
. In the case of a CPU transfer, the address selection field of the local bus control signal
162
is prescribed so that the address on the internal address line
152
is output to the local address bus
135
.
The bus interface
155
decodes the address on the local address bus
135
, and outputs the data on the local data bus
128
to the local memory
156
in accordance with the decoded address.
(DMA Transfer)
The controller
122
outputs the local bus request signal
130
to the bus controller
133
.
If the local bus request signal
160
from the internal data processor
161
has not been asserted, the bus controller
133
outputs the local bus grant signal
129
to the controller
122
.
Upo

Affiliated with

Also associated with

Rating

Data transfer apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data transfer apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data transfer apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3362657