Data synchronization hardware primitive in an embedded...

Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling

Reexamination Certificate

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C718S103000, C711S147000

Reexamination Certificate

active

07137118

ABSTRACT:
An embedded symmetrical multiprocessor system includes arbitration logic that determines which central processing unit has access to shared memory. Upon grant of access, the memory address is stored in a memory address register. An address compare circuit compares the access address of any other central processing unit with this stored address. Upon a match, the arbitration logic stalls the second accessing central processing unit until expiration of a programmable number of wait states following the first access. These wait states give the first central processing unit enough time to determine the state of a lock variable and take control of an operation protected by the lock variable. The application boot code can determine how long the read-check-write operation requires and program that value into the wait-state generator.

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patent: 6009495 (1999-12-01), DeRoo et al.
patent: 6014729 (2000-01-01), Lannan et al.
patent: 6954873 (2005-10-01), Jain
Altera, “System Design Using SOPC Builder” (Dec. 2004).

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