Data synchronization for a test access port

Details Data synchronization for a test access port Data synchronization for a test access port

2007-01-23

2007-01-23

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error detection for synchronization control

C713S500000, C327S153000, C370S416000

Reexamination Certificate

active

09738405

ABSTRACT:
In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

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