Data synchronization circuit and communication interface...

Details Data synchronization circuit and communication interface... Data synchronization circuit and communication interface...

2006-09-05

2006-09-05

Ha, Dac (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000

Reexamination Certificate

active

07103128

ABSTRACT:
There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.

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patent: 59-003544 (1984-01-01), None

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