Data synchronization circuit and communication interface...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S354000

Reexamination Certificate

active

07103128

ABSTRACT:
There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.

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patent: 5077761 (1991-12-01), Tokunaga
patent: 5430772 (1995-07-01), Lee et al.
patent: 6334163 (2001-12-01), Dreps et al.
patent: 6356566 (2002-03-01), Lee et al.
patent: 6437712 (2002-08-01), Aoki
patent: 6542999 (2003-04-01), Dreps et al.
patent: 59-003544 (1984-01-01), None

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