Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
1999-12-30
2001-03-06
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
Reexamination Certificate
active
06198674
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a data strobe signal generator of the SDRAM and DDR SDRAM device.
DESCRIPTION OF THE PRIOR ARTS
Generally, a data strobe signal used in a DRAM device has the same drivability and timing as output data at a read operation and is also used as a signal indicating that the data are output into a CPU and a controller outside the memory chip. When a write operation is carried out, the data strobe signal is input into the DRAM device with the same timing as input data so that the data strobe signal indicates that input data is to be written in a cell.
FIG. 1
is a block diagram illustrating a conventional data strobe signal generator. As shown in
FIG. 1
, the conventional data strobe signal generator includes a pulse generator
100
, a PMOS transistor
101
, a current output state signal generator
102
, first and second pull-up/pull-down signal generators
103
and
104
and a data strobe signal driver
105
. The pulse generator
100
receives a data strobe preamble signal qsen_pre and produces a pulse. The PMOS transistor
101
controls a preamble state of the data strobe signal driver
105
in response to an output from the pulse generator
100
. The current output state signal generator
102
receives first and second pipe counter signals pcnt_even <0:2> and pcnt_odd <0:2> and a data strobe enable signal qsen and produces first and second state signals qsb_even and qsb_odd for outputting a data strobe signal in advance. The first pull-up/pull-down signal generator
103
receiving the first pipe counter signal pcnt_even <0:2>, the data strobe enable signal qsen and the first state signal qsb_even from the current output state signal generator
102
produces pull-up and pull-down signals pu and pd and the second pull-up/pull-down signal generator
104
receiving the second pipe counter signal pcnt_odd <0:2>, the data strobe enable signal qsen and the second state signal qsb odd from the current output state signal generator
102
produces pull-up and pull-down signals pu and pd. The data strobe signal driver
105
outputs a data strobe signal dqs in response to the pull-up and pull-down signals pu and pd.
Referring to
FIG. 2
, a preamble state of the data strobe signal dqs starts when the data strobe preamble signal qsen_pre goes from a logic low state to a logic high state and such a preamble state is over when the data strobe enable signal qsen goes from a logic high state to a logic low state. The pull-up signal pu is activated by the first state signal qsb_even and the first pipe counter signal pcnt_even <0:2> and the pull-down signal pd is activated by the second state signal qsb_odd and the second pipe counter signal pcnt_odd <0:2>.
Referring to
FIG. 3
, the current output state signal generator
102
includes a first pulse generator
300
receiving the first pipe counter signal pcnt_even <0> to produce a pulse, an input unit
301
ANDing the first pipe counter signal pcnt_even <2>, the data strobe enable signal qsen and the second pipe counter signal pcnt_odd <2>, and a second pulse generator
302
receiving the second pipe counter signal pcnt_odd <0> to produce a pulse. Also, the current output state signal generator
102
includes a first output unit
303
receiving outputs from the first pulse generator
300
and the input unit
301
to produce the second state signal qsb_odd <0> and a second output unit
304
receiving outputs from the second pulse generator
302
and the input unit
301
to produce the first state signal qsb_even <0>.
Referring to
FIG. 4
showing a timing chart of each signal in the current output state signal generator
102
, the second state signal qsb_odd <0> is activated by the first pipe counter signal pcnt_even <0> and the first state signal qsb_even <0> is activated by the second pipe counter signal pcnt_odd <0>. Also, the activation of the first and second state signals qsb_even <0> and qsb_odd <0> is terminated at a rising edge of the first pipe counter signal pcnt_even <2>.
Referring to
FIG. 5
, each of the first and second pull-up/pull-down signal generators
103
and
104
includes an input unit
500
and a pull-up and pull-down signal driver
501
. The input unit
500
receives one of the first and second state signals qsb_even <0> and qsb_odd <0>, a signal qs_b, and an output enable signal outen, which is produced by delaying the data strobe enable signal qsen, for NANDing the received signals. The pull-up and pull-down signal driver
501
receives an output from the input unit
500
and one of the first and second pipe counter signals pcnt_even <0:2> and pcnt_odd<0:2>, a signal pcnt_o, and drives the pull-up and pull-down signals pu and pd.
Referring to
FIG. 6
, the data strobe enable signal qsen is activated in a logic high state and the first state signal qsb_even <0> and the first pipe counter signal pcnt_even <0> activate the pull-up signal pu. Also, the second state signal qsb_odd <0> and the second pipe counter signal pcnt_odd <0> enable another pull-up/pull-down signal generator
104
, then produce the pull-down signal pu.
The data strobe signal driver
105
in
FIG. 7
is implemented by a common output buffer employed in a typical data output stage of a semiconductor device so that detail description will be omitted. However, the data strobe signal driver
105
in
FIG. 7
has a latch circuit in its input stage and the latch circuit may be rest by a reset signal outoff. When the pull-up and pull-down signals pu and pd are in a logic low state, the data strobe signal dqs is in a high impedance state, and when one of the pull-up and pull-down signals pu and pd is in a logic high state, the data strobe signal dqs may be outputted. If the pull-up signal pu is activated in a logic high signal, the data strobe signal dqs is output as a high signal and if the pull-down signal pd is activated in a logic low signal, the data strobe signal dqs is output as a low signal.
However, the conventional data strobe signal generator uses the output of the pipe counter, which has been used in a previous operation, in order to produce the data strobe signal to be required in a current data output. Accordingly, in order to use the previously used pipe counter signal, the conventional data strobe signal generator is in need of the current output state signal generator so that a complicated layout and a large area are required.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device occupying a small area of a chip.
It is another object of the present invention to provide a semiconductor memory device with a low-power consumption and a simple layout, by improving a data strobe signal generator.
In accordance with an aspect of the present invention, there is provided a data strobe signal generator in a SDRAM memory device, comprising: a preamble controller for controlling a preamble state of a data strobe signal in response to a control signal; a plurality of pull-up/pull-down signal drivers for producing pull-up and pull-down signals through a toggling operation in response to previous pull-down and pull-up signals; and a data strobe signal driver for outputting the data strobe signal in response to the pull-up and pull-down signals.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:
FIG. 1
is a block diagram illustrating a conventional data strobe signal generator;
FIG. 2
is a timing chart of the conventional data strobe signal generator in
FIG. 1
;
FIG. 3
is a circuit diagram illustrating a current output state signal generator in
FIG. 1
;
FIG. 4
is a timing chart of the current output state signal generator in
FIG. 3
;
FIG. 5
is a circuit diagram illustrating a
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Nguyen Tan T.
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