Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-08-30
2001-08-28
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100
Reexamination Certificate
active
06282132
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to devices and methods to enable data-strobe input buffers to recognize strobe signals for high-frequency synchronous dynamic random access memories.
BACKGROUND
Memory devices are integrated circuits in which information may be stored and from which information may be extracted when desired. Each memory device is built from a plurality of memory cells. Each memory cell memorizes a bit of data. Although a bit of data seems insignificant, it may determine whether the stored information is correct, such as an amount in a checking account.
The process of memorizing the bit of data by the memory cell is an example of the ingenuity of a memory device. Each memory device performs many other feats of engineering. The notion that information may be stored and extracted when desired involves the element of time. Memory device activities are timed to predictively perform according to a train of pulses. This train of pulses can be likened to the gestures of a conductor conducting a symphony. In the parlance of engineering, this train of pulses is known as a clock, and more specifically, the train of pulses is called a strobe when it is used to initiate the passage of data.
To start the process of memorizing the bit of data by the memory cell, a write signal is issued so that the bit of data may be written to the memory cell. The memory device, which houses the memory cell, delays the writing of the bit of data for a period of time until the write signal is validated by an appropriate transition in the strobe. Such a strategy may be fine for memory devices that are designed to work at low speeds, but it creates problems for the proper operation of future generations of memory devices.
Thus, what is needed are devices and methods to recognize the transition of the strobe at an appropriate time so as to enhance the speed of operations of future generations of memory devices, such as synchronous DRAMs (SDRAMs), and specifically, double-data-rate SDRAMs (DDR SDRAMs).
SUMMARY
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Devices and methods are described which accord these benefits.
One illustrative embodiment includes a method for enabling recognition of valid data in an SDRAM. The method comprises analyzing memory commands before a setup time is expired and validating the data to input into the SDRAM. The act of validating occurs when the act of analyzing memory commands enables a circuit to recognize the first rising edge of a strobe so as to validate the data.
Another illustrative embodiment includes another method for enabling recognition of valid data in an SDRAM. The method includes analyzing to issue a write signal before a setup time is expired, enabling a circuit to validate the data if the write signal is issued, and inhibiting the circuit from being enabled if the write signal is issued in the presence of noise.
Another illustrative embodiment includes a device for enabling validation of data in a DDR SDRAM. The device includes an analyzer to analyze commands to produce a write signal and an enabling circuit to produce an enabling signal before the write signal is confirmed to recognize a first rising edge of a strobe so as to validate the data.
Another illustrative embodiment includes a device for enabling validation of data in a DDR SDRAM. The device includes an analyzer to analyze commands to produce a write signal, an enabling circuit to produce the enabling signal, a verifier to confirm the write signal by reproducing the write signal, a latch to latch at least one of an enabling signal and a disabling signal, a disabling circuit to activate a disabling signal when noise is present, and an inverting circuit to drive at least one of the enabling signal and the disabling signal to recognize a first rising edge of a strobe before the verifying circuit confirms the write signal so as to validate the data.
Another illustrative embodiment includes a synchronous DRAM. The synchronous DRAM includes a bank that defines a portion of a memory array, at least one data input buffer that produces one bit of data, and a circuit that executes at least one of two acts. The two acts include enabling and disabling the at least one data input buffer. The act of enabling enables the at least one data input buffer to recognize a first rising edge of a strobe before a write signal is confirmed so as to validate the data within a desired duration.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5349566 (1994-09-01), Merritt et al.
patent: 5812492 (1998-09-01), Yamauchi et al.
patent: 6115314 (2000-09-01), Wright et al.
Brown Jason M.
Penney Daniel B.
Mai Son
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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