Data streaming mechanism in a microprocessor

Details Data streaming mechanism in a microprocessor Data streaming mechanism in a microprocessor

2005-10-18

2005-10-18

Sparks, Donald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S125000, C711S138000, C711S204000, C712S205000, C712S206000, C712S207000

Reexamination Certificate

active

06957305

ABSTRACT:
This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2cache to the CRB in the main CPU, which will bypass the L1data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.

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