Data stream smoothing using a FIFO memory

Details Data stream smoothing using a FIFO memory Data stream smoothing using a FIFO memory

1991-07-17

1992-06-16

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Sipo/piso

365221, 365222, 36523008, G11C 700

Patent

active

051229889

ABSTRACT:
A data stream smoothing circuit wherein a FIFO memory receives data from the DRAM, and a memory status circuit provides a memory-full status signal when the FIFO memory contains a selected amount of data from the DRAM. A refresh timer generates a refresh request signal whenever DRAM refresh should be performed. When the refresh request signal is generated, a refresh control circuit refreshes a row of data in the DRAM upon occurrence of the next memory-full status signal.

REFERENCES:
patent: 4631701 (1986-12-01), Kappeler et al.
patent: 4642797 (1987-02-01), Hoberman
patent: 4777624 (1988-10-01), Ishizawa et al.
patent: 4882710 (1989-11-01), Hashimoto et al.
patent: 4891788 (1990-01-01), Kreifels

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