Data stream frequency reduction and/or phase shift

Details Data stream frequency reduction and/or phase shift Data stream frequency reduction and/or phase shift

2007-12-25

2007-12-25

Fan, Chieh M. (Department: 2611)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C712S300000, C710S305000, C713S400000, C341S100000, C341S061000, C436S094000

Reexamination Certificate

active

10656195

ABSTRACT:
A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number, which establishes a de-serialization level for frequency reduction or phase shifting. An output provides an output data stream at the desired output frequency.

REFERENCES:
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patent: 5128940 (1992-07-01), Wakimoto
patent: 5864309 (1999-01-01), Hung
patent: 6228656 (2001-05-01), Ishiguro et al.
patent: 6696995 (2004-02-01), Foley et al.
patent: 6996650 (2006-02-01), Calvignac et al.
patent: 7065665 (2006-06-01), Jacobson et al.
patent: 2004/0015666 (2004-01-01), Rojas et al.

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