Data storing method of dynamic RAM and semiconductor memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S763000

Reexamination Certificate

active

07051260

ABSTRACT:
When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

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Berger, “A Note on Error Detection Codes for Asymmetric Channels”, Information and Control, vol. 4, pp. 68-73 (1961).

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