Data storage system having row/column address parity checking

Details Data storage system having row/column address parity checking Data storage system having row/column address parity checking

1996-08-23

1999-09-21

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

714821, 714 53, G06F 702

Patent

active

059548380

ABSTRACT:
An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit. Each one of the memory units includes: a buffer memory coupled to the bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus.

REFERENCES:
patent: 3599146 (1971-08-01), Weisbecker
patent: 3944800 (1976-03-01), Beck et al.
patent: 4020459 (1977-04-01), Coomer
patent: 4050059 (1977-09-01), Williams et al.
patent: 4295219 (1981-10-01), Draper et al.
patent: 5206939 (1993-04-01), Yanai et al.
patent: 5392302 (1995-02-01), Kemp et al.

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