Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1998-12-30
2003-03-25
Wong, Peter (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S305000, C710S241000, C710S110000, C710S039000, C714S042000, C714S043000, C714S044000
Reexamination Certificate
active
06539451
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers (or directors) and “back end” disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus.
SUMMARY OF THE INVENTION
In accordance with the invention, an arbiter is electrically connected to each one of the busses.
In accordance with another feature of the invention, the arbiter is connected to an end of the busses.
In accordance with another feature of the invention, a second arbiter connected to another end of the bus, the arbiter connected to one end of a bus being a master arbiter and the arbiter connected to the other end of the bus being a slave arbiter. The master arbiter provides arbitration between directors connected to the bus and, if one of the directors connected to such bus indicates a fault, the master arbiter is disabled and the slave arbiter is enable to provide such arbitration.
In accordance with another feature of the invention, the system includes a printed circuit board having the plurality of busses and a plurality of electrical connectors arranged in a linear array and electrically connected to the busses. The electrical connectors are adapted to receive the directors on one side of the printed circuit board and adapter cards on the other side of the printed circuit board. The directors and adapter cards received in a common one of the electrical connectors are electrically connected by pins passing from one side to the other side of the printed circuit board. Adapter cards connected to the terminating ends of a bus, and received in end ones of the electrical connectors, have thereon the master arbiter and slave arbiter. Pins in the electrical connectors at the ends of the bus are adapted to receive either an adapter card having the master arbiter or an adapter card having the slave arbiter. The electrical connector at one end of the bus has a reference electrical potential on a pin thereof and the electrical connector at the other end of the bus has a high impedance thereon on a pin thereof. The pins are in the same position of both electrical connectors. When the adapter cards are received by the electrical connectors, the reference electrical potential at the pin configures the adapted card connected thereto into one of the master or slave arbiters and the high impedance at the pin configures the adapted card connected thereto into the other one of the master or slave arbiters.
In accordance with another feature of the invention, each one of the directors is adapted to produce on the bus coupled thereto a plural bit priority code. Each one of the arbiters is responsive to the priority code of the directors coupled thereto and assigns access to such bus coupled to such directors selectively in accordance with a predetermined criteria.
SUMMARY OF THE (Vref GENERATION) INVENTION
In accordance with another feature of the invention, a plurality of reference voltage generators is provided, each being electrically connected to a corresponding one of the buses. The bus couples the generated reference voltage to each one of the directors electrically connected to such bus. Each one of the directors electrically connected to the bus includes a reference voltage receiver response to the generated reference voltage for distributing the generated reference voltage among electrical components in such director.
In accordance with another feature of the invention, a pair of reference voltage generators is electrically connecting to ends of a corresponding one of the busses.
In accordance with another feature of the invention, the reference voltage generator includes a input section adapted to vary the reference voltage produced by the reference voltage generator.
In accordance with another feature of the invention, the input section comprises a digital to analog converter.
REFERENCES:
patent: 5206939 (1993-04-01), Yanai et al.
patent: 5699533 (1997-12-01), Sakai
patent: 5815680 (1998-09-01), Okumura et al.
patent: 5839906 (1998-11-01), Leshem
patent: 6141713 (2000-10-01), Kang
patent: 6145042 (2000-11-01), Walton
patent: 6195770 (2001-02-01), Walton
patent: 6230229 (2001-05-01), Van Krevelen et al.
patent: 6272591 (2001-08-01), Grun
Dellicicchi Alfred
Romano Scott
Zani Mark
Daly, Crowley & Mofford LLP
EMC Corporation
Phan Raymond N
Wong Peter
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