Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-10-17
2006-10-17
Padmanabhan, Mano (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S004000
Reexamination Certificate
active
07124245
ABSTRACT:
A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. The cache memory manager, plurality of front end directors, plurality of back end directors and cache memory are interconnected through a packet switching network.
REFERENCES:
patent: 5214768 (1993-05-01), Martin
patent: 5903911 (1999-05-01), Gaskins
patent: 5920893 (1999-07-01), Nakayama et al.
patent: 6009481 (1999-12-01), Mayer
patent: 6216199 (2001-04-01), DeKoning et al.
patent: 6606715 (2003-08-01), Kikuchi
patent: 6611879 (2003-08-01), Dobecki
patent: 6651130 (2003-11-01), Thibault
patent: 2002/0184441 (2002-12-01), Wong et al.
patent: 2003/0009643 (2003-01-01), Arimilli et al.
patent: 2003/0135674 (2003-07-01), Mason et al.
patent: 2004/0010659 (2004-01-01), Inoue
Microsoft Computer Dictionary, 2002, Microsoft Press, Fifth Edition, p. 334.
U.S. Appl. No. 10/180,751, filed Jun. 26, 2002.
Baxter, III William F.
Bermingham Michael
Castel Daniel
Chilton Kendell A.
Guyer James M.
EMC Corporation
Padmanabhan Mano
Rojas Midys
LandOfFree
Data storage system having cache memory manager with packet... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data storage system having cache memory manager with packet..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data storage system having cache memory manager with packet... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3714510