Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1996-08-23
2002-02-12
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000, C711S148000, C713S400000, C713S500000, C713S600000, C714S005110
Reexamination Certificate
active
06347365
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers and “back end” disk controllers. The interface operates the controllers in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yansi, Natan Vishlitzky, Bruno Altersu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent the interface may also include, in addition to the CPU controllers and disk controllers, addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses.
Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail.
In one system, the communication to the controllers and the cache memories is through a pair of bi-directional lines. Typically one bi-directional line is for data and the other bi-directional line is for control signals. As noted above, each controllers is connected to only one of the buses and, therefore, only one pair of bi-directional lines are electrically connected to the controllers; however, because each one of the cache memories is connected to both buses, each cache memory has two pairs of bi-directional lines.
One such data storage system is an asynchronous system. In such system, when a controller wishes to read data from an addressed memory, the addressed memory places the data and a clock pulse on the bus. The data and the clock travel along the bus to the controller, the controller receives the data and clocks the data into the controller using the clock placed on the bus by the addressed memory. When the controller wishes to have data written into an addressed memory, the controller places the data on the bus and the addressed memory must strobe the data on the bus into itself. However, because the system is asynchronous, the addressed memory may not be ready to accept the data on the bus. Therefore, when addressed by the controller, the memory places a clock on the bus, the clock runs to the controller, the controller detects the clock sent by the addressed memory and places the data on the bus. The data runs back to the addressed memory, and then, after a predetermined round-trip time, the addressed memory clocks in the data. While the round-trip is a function of the distance between the controller and the addressed memory, the system is designed with the a predetermined round-trip time sufficient to account for the maximum expected round-trip time. Thus, in those cases where the controller/addressed memory pair are relative close together, time is lost in waiting for the maximum predetermined round-trip time before the addressed memory writes in the data on the bus.
SUMMARY OF THE INVENTION
In accordance with one feature of the invention, an addressable memory is provided having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transfer data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus.
With such an arrangement, improved data transfer to and from such memory is achieved.
In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO).
In accordance with another feature of the invention, a data storage system is provided wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit. Each one of the memory units includes: a buffer memory coupled to the bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network coupled to the bus and configured to transfer data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus.
In accordance with another feature of the invention, an addressable memory is provided having a master memory unit and a slave memory unit. The master memory unit and the slave memory unit have the same address as the addressable memory. A control unit is provided for producing control signals to enable data stored in the master memory unit to be read therefrom and transferred to the bus when such data is requested from the addressable memory and to enable data on the bus to be written into both the master memory unit and the slave memory unit when data on the bus is to be written into the addressable memory.
With such an arrangement, each addressable memory has redundancy and is operable in case either the master memory unit or the slave memory unit thereof fails.
In accordance with another feature of the invention, the control unit is adapted to: (i) during a normal mode, enable data produced on the bus to be written into both the master memory unit and the slave memory unit and data in only the master memory unit to be read therefrom when such data is to be transferred to the bus, and (ii) during a read/copy mode, enable data stored in the master memory unit to be read therefrom, transferred to the bus, and written from the bus into the slave memory unit.
With such an arrangement, data in the master memory unit may be copied to the slave memory unit during the read/copy mode without disrupting the operation of the system after a failed slave
Leshem Eli
Walton John K.
Daly, Crowley & Mofford LLP
EMC Corporation
Kim Matthew
Vital Pierre M.
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