Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1998-12-30
2001-05-08
Lee, Thomas (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S120000, C711S100000, C711S105000, C711S154000
Reexamination Certificate
active
06230221
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers (or directors) and “back end” disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus.
SUMMARY OF THE INVENTION
In accordance with the invention, a plurality of reference voltage generators is provided, each being electrically connected to a corresponding one of the buses. The bus couples the generated reference voltage to each one of the directors electrically connected to such bus. Each one of the directors electrically connected to the bus includes a reference voltage receiver response to the generated reference voltage for distributing the generated reference voltage among electrical components in such director.
In accordance with another feature of the invention, a pair of reference voltage generators is electrically connecting to ends of a corresponding one of the busses.
In accordance with another feature of the invention, the reference voltage generator includes a input section adapted to vary the reference voltage produced by the reference voltage generator.
In accordance with another feature of the invention, the input section comprises a digital to analog converter.
REFERENCES:
patent: 5206939 (1993-04-01), Yanai et al.
patent: 5889699 (1999-03-01), Takano
patent: 5948062 (1999-09-01), Tzelnic et al.
patent: 5996042 (1999-11-01), Pawlowski et al.
patent: 6072730 (2000-06-01), Becker et al.
Bisbee David
Mulvey Christopher
Daly, Crowley & Mofford LLP
EMC Corporation
Lee Thomas
Perveen Rehana
LandOfFree
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