Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
1998-12-30
2001-09-11
Lee, Thomas (Department: 2751)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S120000, C711S111000, C361S689000
Reexamination Certificate
active
06289401
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers (or directors) and “back end” disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus.
SUMMARY OF THE INVENTION
In accordance with the present invention, a data storage system is provided wherein a host computer is coupled to a bank of disk drives through a system interface. The system interface includes a memory having a high address memory section and a low address memory section. A plurality of directors controls data transfer between the host computer and the bank of disk drives as such data passes through the memory. A pair of high address busses is in communication with the high address memory section and a pair of low address busses is in communication with the low address memory section. Each one of the directors is in communication with one of the pair of high address busses and one of the pair of low address busses.
In accordance with another feature of the invention, the system interface includes a printed circuit board having a plurality of electrical connectors arranged in a linear array and electrically connected to the busses. The electrical connectors are adapted to receive the directors and the memory and electrically interconnect the directors and memory received therein to the busses. A first set of the directors is electrically connected to a first pair of the busses and a second set of directors interleaved with the first set is electrically connected to a second pair of the busses.
In accordance with still another feature of the invention, each one of the electrical connectors has three sections. For the electrical connectors which receive the first set of directors, such electrical connectors have a first one of the three section connected to a first one of the busses in the first pair of busses and a second one of the three sections connected to a second one of the busses in the first pair of busses. For the second set of directors, the electrical connectors have the first one of the three section connected to a first one of the busses in the second pair of busses and the second one of the three sections connected to a second one of the busses in the second pair of busses.
In accordance with another feature of the invention, for the electrical connectors which receive memory sections, one such electrical connector has the first one of the three section connected to the first one of the busses in the first pair of busses and a third one of the three sections connected to the second one of the busses in the second pair of busses. Another one of the electrical connectors connected to a memory section has the first one of the three section connected to the second one of the busses in the first pair of busses and the third one of the three sections connected to the second one of the busses in the second pair of busses.
In accordance with still another feature of the invention, the printed circuit board includes a universal electrical connector adapted to receive either a director or a memory. The universal electrical connector has the three section. The first section of the connector is connected to either the first one of the busses in the first pair thereof or to the first one of the busses in the second pair thereof. The second section of the connector is connected to either the second one of the busses in the first pair thereof or to the second one of the busses in the second pair thereof. The third section of the connector is connected to the second one of the busses in the second pair thereof or to the second one of the busses in the first pair thereof.
REFERENCES:
patent: 5113496 (1992-05-01), McCalley et al.
patent: 5206939 (1993-04-01), Yanai et al.
patent: 5536989 (1996-07-01), Skudera, Jr.
patent: 5560027 (1996-09-01), Watson et al.
patent: 5719885 (1998-02-01), Ofer et al.
patent: 5839906 (1998-11-01), Leshem
patent: 6145042 (2000-11-01), Walton
patent: 6195770 (2001-02-01), Walton
Khan Farouk
Mulvey Christopher
Tuccio William
Daly, Crowley & Mofford LLP
Du Thuan
EMC Corporation
Lee Thomas
LandOfFree
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