Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-12-30
2002-12-10
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C710S048000, C710S305000, C711S147000, C711S154000, C711S162000
Reexamination Certificate
active
06493795
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers (or directors) and “back end” disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a system bus made up of a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus.
SUMMARY OF THE INVENTION
In accordance with the present invention, a data storage system is provided wherein a host computer is coupled to a bank of disk drives through an interface. The interface includes a system memory comprising a pair of system memory sections. Each one of the memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A system bus is coupled to the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus, such directors being configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory. The directors are configured to place the system in a dual-write mode, and in such mode, store therein a burst of the data to be transferred between the host computer and the bank of disk drives, transfer such stored burst of data sequentially to the system bus, and enable both of the memory sections coupled to such system bus to have written therein, at the same one of the addressable locations, the same burst of data transferred sequentially to the system bus.
In accordance with another feature of the invention, the interface includes a system memory having a pair of system memory sections. Each one of the system memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A system bus comprising a pair of system busses is provided, each one of the pair of system busses being coupled to a corresponding one of the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus. The directors are configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory. The directors are configured to place the system in a dual-write mode, and in such mode, store therein a burst of the data to be transferred between the host computer and the bank of disk drives, transfer such stored burst of data sequentially to the pair of system busses, and enable both of the system memory sections coupled to such pair of system busses to have written therein, at the same one of the addressable locations, the same burst of data transferred sequentially to the pair of system busses.
In accordance with another feature of the invention, during the dual-write mode, the directors store therein bursts of the data to be transferred between the host computer and the bank of disk drives. Each burst of data stored in the director is then transferred to one of the pair of system busses coupled to such director during one memory cycle and, during the next memory cycle, the same burst of data is then transferred again, but this time to the other one of the pair system busses coupled to such director. Thus, the same stored burst of data is transferred sequentially to both the pair of system busses coupled to such director. The director sequentially enables both of the memory sections coupled to both such pair of system busses to have written therein, at the same addressable locations, the same data burst which had been sequentiality transferred to each of the pair of system busses coupled to the director. Thus, after the pair of system memory cycles, the burst of data and a copy of such burst of data are stored in the same addressable location of both memory sections. Consequently, redundant data bursts are stored in the system memory.
In accordance with another feature of the invention, a dual-write bus is coupled to the plurality of directors. Each one of the directors includes: (a) a director memory for storing the burst of data fed thereto from the either the host computer or the bank of disk drives; and, (b) a dual-write controller. The dual-write controller is adapted to: (i) provide a dual-write interrupt on the dual-write bus in response to a dual-write mode command fed to the system; (ii) receive a dual-write interrupt produced on the dual-write bus; and (iii) in response to the dual-write interrupt received on the dual-write bus, sequentially place the burst of data stored in the director memory on the pair of system busses for sequential storage in both of the system memory sections at the same one of the addressable locations.
In accordance with still another feature of the invention, the system is adapted to return to a non-dual-write mode when each of the plurality of directors is reset to a non-dual-write mode in response to a reset condition provided to the system. When returned
Arsenault Brian
Kinne Jeffrey Stoddard
Tung Victor W.
Chace C. P.
Daly, Crowley & Mofford LLP
EMC Corporation
Kim Matthew
LandOfFree
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