Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-11-28
2006-11-28
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S037000, C710S038000
Reexamination Certificate
active
07143306
ABSTRACT:
A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.
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Bruno Eric J.
Campbell Brian K.
Porat Ofer
Wilson Paul C.
Xu Jane
Baderman Scott
EMC Corporation
Truong Loan
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