Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1998-06-05
2001-07-10
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S140000, C711S154000, C711S169000
Reexamination Certificate
active
06260126
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to data storage subsystems and, more particularly, to a method and apparatus for enabling a data storage subsystem to perform housekeeping data processing functions during an input/output data transfer.
BACKGROUND OF THE INVENTION
Currently, data storage subsystems (DSSs) are configured as arrays of disk drives which provide high capacity storage for one or more attached host processors. Each host processor is coupled to the DSS via a high capacity communication channel and a dedicated front-end processor at the DSS. The front-end processor performs the command and protocol processing to facilitate the data transfers. However, when the actual data transfer occurs, it often by-passes the front-end processor and is performed as a “direct memory access” (DMA). Under such circumstances, the input data flows directly from the host processor to a cache memory in the DSS or from the cache memory in the DSS to the host processor, in both cases bypassing any buffering by the front-end processor. During a DMA, the front end processor is idle.
The prior art has suggested that such front end processors be applied to other functions during a DMA input/output data transfer action. U.S. Pat. No. 4,400,772 to Broyles et al., entitled “Method and Apparatus for Direct Memory Access in a Data Processing System” suggests that during a DMA, the central processing unit be placed in an idle state, without disturbing the central processing unit registers. This enables the central processing unit to then carry out secondary functions. One such suggested secondary function is to continue the refreshing of dynamic memory used in the system.
When a DSS processor, in a system such as described above by Broyles et al. remains idle, typically, the operating system relinquishes control of the DSS processor and makes it available for a new task. However, there is no guarantee how long the new task will take to execute. In such a case, if the DSS processor is occupied with the new task and the host processor's input/output operation finishes, the system remains in a wait state until the DSS processor again becomes available to perform an input/output function. This action may slow the system's primary function, i.e., input/output of data from/to the host processor. Only when the DSS processor becomes available to process the necessary command and interface data can an input/output action be accommodated.
Accordingly, it is an object of this invention to provide a method and apparatus for control of a DSS which enables a front end processor to be utilized for other tasks during an input/output data transfer.
It is another object of this invention to assure that the front-end processor of a DSS is available for use with an input/output action at the end of an input/output data transfer, irrespective of what other tasks have been assigned to it to be carried out.
SUMMARY OF THE INVENTION
The invention implements a method for enabling overlapped performance of data processing actions during data transfers between a DSS and a host processor. The DSS includes a state queue which holds a plurality of states, each state comprising a self-contained procedure which, upon execution, determines a readiness to execute of an associated task. The method initially determines an amount of available time during a data transfer wherein a front-end processor of the DSS would otherwise be idle. The method then causes the front-end processor to extract and execute a first state from the state queue during the data transfer, if available time during the data transfer exceeds or is equal to an estimated execution time of the first state. Then, if a task associated with the first state is found to be ready to execute, that task is listed on a task work queue for execution subsequent to the data transfer. If, after execution of the first state, additional time remains, further states may be executed, in each instance, however, care being taken to assure that the front-end processor is ready to accommodate a new input/output operation when the current input/output operation ends.
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International Busines Machines Corporation
Krall Esq. Noreen
Ohlandt Greeley Ruggiero & Perle LLP
Thai Tuan V.
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