Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-06-28
2003-12-30
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S117000
Reexamination Certificate
active
06671199
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a capacitor as a charge storage capacitor, a data storage method for a semiconductor integrated circuit equipped with switching elements as transfer gates, a semiconductor integrated circuit, a semiconductor device equipped with many of the semiconductor integrated circuits, and an electronic apparatus using the semiconductor device.
2. Conventional Technology
FIG. 12
shows a block diagram of a conventional structure of a semiconductor integrated circuit including a charge storing ferroelectric capacitor. To simplify the description, only two memory cells
1
,
2
are shown in the circuit diagram in FIG.
12
.
First, the circuit structure is described. The memory cells
1
and
2
include capacitors
6
and
8
as charge storing capacitors formed from ferroelectric material, and Nch transistors
5
and
7
as switching transfer gates, respectively. A bit line BL and a plate line PL are commonly connected to the respective memory cells
1
and
2
, and independent word lines WL
1
and WL
2
are connected to gates of the Nch transistors
5
and
7
, respectively. The bit line BL is connected to a sense amplifier
3
for data reading and to a restore/write circuit
4
.
Next, a writing operation of the semiconductor integrated circuit is described.
In order to write in the memory cell
1
, a bit line potential VBL and a plate line potential VPL are set at a grounding potential (hereinafter, GND potential), then the GND potential on the word line WL
1
is shifted to a power supply potential VDD to thereby put the transistor
5
in an ON state.
When data is H data, the restore/write circuit
4
sets the bit line potential VBL to the power supply potential VDD, and the plate line potential VPL to the GND potential, whereby an electric field directing from the bit line toward the plate line is applied to the capacitor
6
, and a charge (data) associated with a polarization corresponding to the strength and the direction of the electric field is written in the ferroelectric capacitor
6
.
When data is L data, the bit line potential VBL is shifted to the GND potential, and the plate line potential VPL to the power supply potential VDD, whereby an electric field directing from the plate line toward the bit line is applied to the capacitor
6
, and a charge (data) associated with a polarization corresponding to the strength and the direction of the electric field is written in the ferroelectric capacitor
6
.
Then, the power supply potential VDD on the word line WL
1
is shifted to the GND potential to thereby place the transistor
5
in an OFF state to retain the written data and complete the writing operation.
On the other hand, for the memory transistor
2
, the word line WL
2
is retained at the GNP potential to put the transistor
7
in an OFF state and a writing operation is not conducted.
Next, a reading operation of the semiconductor integrated circuit is described.
In order to read the memory cell
1
, the bit line potential VBL and the plate line potential VPL are set at the GND potential, and then the GND potential on the word line WL
1
is shifted to the power supply potential VDD to thereby put the transistor
5
in an ON state. Then, when the plate line potential VPL is shifted to the power supply potential VDD, a potential corresponding to a charge (data) associated with the polarization retained in the ferroelectric capacitor
5
is generated on the bit line BL. When a reference level VREF of the sense amplifier
3
is set at an intermediate value between bit line potentials to be generated corresponding to H level and L level of data, data corresponding to H level or L level is amplified and outputted by the sense amplifier
3
.
Then, when data is H data, the restore/write circuit
4
shifts the bit line potential VBL to the power supply potential VDD, and the plate line potential VPL to the GND potential to thereby conduct a restore operation.
When data is L data, the bit line potential VBL is shifted to the GND potential, and the plate line potential VPL to the power supply potential VDD to thereby conduct a restore operation.
In the conventional semiconductor integrated circuit described above, its memory cell is formed from two elements that are one transistor and one capacitor, and therefore its memory cell area becomes large compared to, for example, a flash memory in which its memory cell is formed from one transistor. Therefore, a ferroelectric memory (FeRAM: Ferroelectric Random-access Memory) has a substantially small capacity compared to a flash memory and is difficult to provide a larger capacity.
One of the sources of the problem is that, for storing data, one memory cell can store only one bit data.
The present invention has been made to solve this problem, and its object is to retain data of two bits or greater (multiple values) in one memory cell to thereby increase the degree of effective integration and to facilitate obtaining a larger capacity.
SUMMARY OF THE INVENTION
In a data storage method for a semiconductor integrated circuit in accordance with an embodiment of the present invention, in a memory cell equipped with a ferroelectric material that stores data depending on a polarization state determined by an applied voltage and a direction of the voltage, different voltages in the number of at least two values or greater are applied for each of the directions of the applied voltages to store data
Also, a semiconductor integrated circuit in accordance with an embodiment of the present invention is equipped with a memory cell including a ferroelectric capacitor for storing a charge, and an n-type switching transistor for storing or discharging the charge. One of the electrodes of the capacitor connects to a plate line, and the other of the electrodes connects to one of source/drain of the n-type transistor. A bit line is connected to the other of source/drain of the n-type transistor. The bit line is connected to a sense amplifier circuit for reading data and the data writing circuit and the plate line is connected to the data writing circuit. The n-type transistor has a gate that is connected to a word line for selecting a memory cell, through which voltage is applied to drive the transistor on and off. In the semiconductor integrated circuit described above, a plurality of voltage values are applied by the data writing circuit between the bit line and the plate line, to thereby store charges in the capacitor according to the voltage values to thereby store a plurality of data.
Furthermore, an electronic apparatus in accordance with one embodiment of the present invention is equipped with the above-described semiconductor device.
REFERENCES:
patent: 5038323 (1991-08-01), Schwee
patent: 5668753 (1997-09-01), Koike
patent: 5668754 (1997-09-01), Yamashita
patent: 5991188 (1999-11-01), Chung et al.
patent: 6449184 (2002-09-01), Kato et al.
patent: 2001/0053087 (2001-12-01), Kato et al.
patent: 2002/0006052 (2002-01-01), Kato et al.
patent: 2002/0145903 (2002-10-01), Hasegawa
Harness & Dickey & Pierce P.L.C.
Nguyen Viet Q.
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