Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-12-27
2003-05-27
Peikari, B. James (Department: 2186)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S005110, C711S162000
Reexamination Certificate
active
06571350
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data handling system having a redundant storage configuration. More particularly, the present invention relates to a data storage suitable for averaging workload and for matching contents between storage devices having duplicate data respectively, and constituting a redundant storage arrangement.
Japanese Laid-open Patent Application No. 06-259336 discloses a technique for matching contents between a master extended storage and a sub extended storage both of which constitute a redundant storage configuration. The disclosed technique involves matching the order in which to perform store operations on the master and the sub extended storage devices in order to keep contents identical between the master and the sub extended storage devices. However, the disclosure contains no reference to fetch operations on the master and the sub extended storage devices.
SUMMARY OF THE INVENTION
One way of increasing the speed of data handling systems is by resorting to the so-called cache memory scheme. The cache memory is a high-speed memory having a smaller capacity than a main storage or other types of storage. As such, the cache memory accommodates data that are frequently used. When desired data are found in the cache memory (this case is described as “cache hit” below), the amount of time required to access the data is short because the target data are accessed by simply referencing the cache memory. When the desired data are not found in the cache memory (that case is described as “cache miss” below), it becomes necessary to access the main memory or other appropriate memory where the data should reside. Since there is a large difference in data access time between the case where the target data are found in the cache memory (i.e. cache hit) and the case where the data are not in the cache memory (i.e. cache miss), the effective data access time may be shorted by having frequently referenced data held in the cache memory. So far, however, there have been few known ways of maintaining redundant storage performance when a cache miss has occurred in one or more of the storage devices constituting the redundant storage configuration.
It is known to provide processors each incorporating a cache memory whose contents reflect those of a storage area of the main storage or other types of storage. Each of these processors causes data in its cache memory to be invalidated when data in the storage are updated by any other processor, so as to prevent a mismatch in contents between the cache memory and the storage. However, there have been few references to ways of making coherence control more effective between the cache memory and the storage where a redundant storage configuration is involved.
A first problem to be solved by the present invention involves making even the workload between a master storage and a sub storage. A store operation needs to be performed on all of the master storage and the sub storage to maintain data coherency therebetween, and a fetch operation need only be carried out on the master storage. In such cases, the workload on the master storage is greater than that on the sub storage. When the master storage and the sub storage have identical capabilities, the throughput of the entire storage arrangement is necessarily dependent on the performance of the master storage. If it is possible to even out the workload between the master storage and the sub storage, then the storage configuration as a whole will provide higher throughput than before.
A second problem to be solved by the present invention involves maintaining operational consistency between the master storage and the sub storage. In one example, fetch requests may be issued only to the master storage. In another example, with multi-storage devices incorporating a cache memory each, any one store request may have a cache hit in one storage but may result in a cache miss in the other storage. In such cases, the operation on the master storage and that on the sub storage are differently timed. This can disrupt operational consistency between the master storage and the sub storage. The technique disclosed in the above-cited Japanese Laid-open Patent Application No. 06-259336 involves unilaterally sequencing store operations into the same order for both the master extended storage and the sub extended storage. This technique appears to ensure the execution of redundant operations, except that a decline in performance can arise from the fact that store requests to different addresses are also kept in sequence. That is, when the preceding store request resulted in a cache miss in the sub storage alone, the ensuing store request to the sub storage must wait to be processed even if the latter store request has a cache hit.
A third problem to be solved by the present invention involves making even the cache miss processing time between a redundant storage configuration and non-redundant storage configuration having one or more storage devices each having a cache memory. Suppose that in the redundant storage configuration having a master storage and a sub storage each incorporating a cache memory, a store request results in a cache miss in all of the master storage and the sub storage. In that case, cache miss processing for the master storage is first completed, followed by cache miss processing for the sub storage. Accordingly, in the redundant storage configuration, the cache miss processing takes twice the time it takes in the non-redundant storage configuration.
A fourth problem to be solved by the invention is related to data coherence control between data in the storage devices, and data in cache memories incorporated in each processor. Where a redundant storage control scheme is in effect, the processors should be issued a minimum of invalidation requests to ensure data coherence with multi-storage devices constituting a redundant storage configuration. Suppose that a processor has changed data at an address in a storage. When the data at that address are also found in the cache memory of any other processor, the data need to be invalidated. In such a case, the multi-storage devices with respect to the processors may each issue an invalidation request, which is redundant.
In solving the first problem above and according to one aspect of the present invention, there is provided a data storage having separate storage devices, in which duplicate data are stored, respectively. In the data storage, in response to at least two fetch requests from the processing device, which two fetch requests are to fetch different first and second desired data out of the duplicate data, respectively, wherein the first desired data is fetched from one of the separate storage devices and the second desired data is fetched from the other of the separate storage devices. Accordingly, workload can be substantially averaged between the separate storage devices even if fetch operations are carried out on only one of the separate storage devices.
In solving the second problem above and according to another aspect of the invention, there is provided a data storage having separate storage devices, in which duplicate data are stored, respectively, for sequencing store requests and storing each desired data at the same address in all of the separate storage devices with the same sequenced order. This arrangement makes it possible to ensure data coherency between the separate storage devices even if their operations are differently timed. For example, when the preceding request resulted in a cache miss, a subsequent request to a different reference address may start being processed before the processing of the preceding request is completed.
In solving the third problem above and according to a further aspect of the invention, there is provided a data storage having separate storage devices, in which duplicate data are stored, respectively, and separate second storage devices corresponding to the separate storage devices, respectively, and having a copy of a part of data stored in corres
Kawamura Toshiaki
Kurokawa Hiroshi
Mihashi Shinichi
Yamada Hiroshi
Mattingly Stanger & Malur, P.C.
Peikari B. James
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