Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-02-16
2003-05-27
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S165000, C365S185290
Reexamination Certificate
active
06571312
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a memory having a plurality of erasure-unit regions in which data are erased or written in predetermined units, and more particularly, to a data processing device using, e.g., flash memory.
Flash memory corresponds to semiconductor memory in which data can be electrically written or from which data can be electrically erased. Flash memory is characterized by the ability to retain memory contents without a power supply. Particularly in the field of industrial computers, flash memory is often used as a storage medium, substituting a hard disk.
However, new data cannot be written directly in flash memory. More specifically, data must be collectively erased in units of, for example 64K (Kilobytes) (hereinafter referred to as “erasure units”), before new data is written in the flash memory. After data has been erased in erasure units, new data corresponding to the size of the erased data is written, thus rewriting the data stored in the flash memory.
Particularly, from a structural viewpoint, in large-capacity and high-density flash memory, an erasure unit is larger than the unit for rewriting (hereinafter referred to as a “rewriting unit”). For this reason, in many cases, data used for rewriting is greater in size than the erasure unit. Even in a case where such data is rewritten into the flash memory, data must be erased in erasure units, which may comprise data segments that do not need to be rewritten, and the data containing the erased data segments must be written into the flash memory again.
A technique for rewriting data in flash memory is described in the Unexamined Japanese Patent Application Publication Kokai No. Hei 5-233478.
FIG. 18
is a block diagram showing the schematic of the background art. The operation of the circuit will now be described with reference to FIG.
18
.
This circuit consists of a Central Processing Unit (CPU)
1
, an Erasable Programmable Read-Only Memory (EPROM)
2
, and Static Random Access Memory (SRAM)
3
, and Flash Random Access Memory (FRAM)
4
, a register
5
, and an address bus
9
and a data bus
10
which connect them. The register
5
is used to save the information of the FRAM
4
. Further, the CPU
1
is connected to an FRAM rewritten information transfer terminal
7
and an FRAM rewritten information file
8
through an RS232C line
6
, and the terminal
7
is operated to send the rewritten information in the file
8
to the CPU
1
. Further, information, before the FRAM
4
is all erased or rewritten, is saved in the register
5
temporarily. The saved information is then returned into the FRAM
4
from the register
5
after the FRAM
4
is rewritten.
A data rewriting operation of FRAM
4
will be described. Data that is to be rewritten into the FRAM
4
is downloaded into SRAM
3
. Data pertaining to an area of the FRAM
4
that is not subjected to rewriting is copied to a register
5
. All the contents of the FRAM
4
are deleted by a FRAM clear program stored in EPROM
2
. The data that has been downloaded into the SRAM
3
is copied to the FRAM
4
. Further, the data that has been saved in the register
5
is copied to the original area on the FRAM
4
.
In the prior art, in a case where volatile memory is used as the register
5
which acts as an area into which data are saved at the time of rewriting of the flash memory, in the event that supply of power to the data processing device is interrupted after erasure of data, data pertaining to an area not to be subjected to rewriting, as well as data pertaining to an area to be subjected to rewriting, are lost, thus deteriorating the reliability of flash memory.
In order to prevent loss of the data recorded in the register, the data must be written into flash memory immediately. From an operational viewpoint, flash memory must be erased every time the data stored in flash memory is rewritten. Eventually, the flash memory must be subjected to the number of erasing operations corresponding to the number of times data is rewritten. A limitation, however, is imposed on the number of times flash memory can be subjected to erasure (usually 100,000 times or thereabouts). The number of times that flash memory is subjected to erasure, however, is increased in the prior art, shortening the life of the flash memory. Thus, the number of times the flash memory is subjected to erasure must be decreased.
Therefore, it is an object of the present invention to overcome the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve such problems of the prior art and is aimed at providing a data processing device which prevents erasure of data from flash memory, when the data recorded in the flash memory is rewritten, and further exhibits improved reliability when data is written into the flash memory.
A further object of the present invention is to provide a data processing device that minimizes the number of times that flash memory is subjected to erasure. This is achieved through the use of a simple structure, which maintains reliability, when a limitation is imposed on the number of times that flash memory can be subjected to erasure.
Accordingly, a data storage method for rewriting data into a memory is provided. Write data is written to an erasure block buffer, which comprises a first region of a nonvolatile memory. Non-changing data is copied from the memory to the erasure block buffer, whereby the memory has a plurality of erasure-unit regions and the non-changing data is written in predetermined units. An erasure unit number is recorded to an erasure-unit-number hold region, the erasure-unit-number hold region comprising a second region of the non-volatile memory. Non-changing data is then erased only from the erasure-unit regions, which are to be rewritten. A status of the erasure unit number is determined, and the non-changing data and the write data is transferred from the erasure block buffer to the erasure-unit region in the memory, depending on the status of the erasure unit number. If an interruption of the transferring step occurs, the transferring step is resumed in response to the status of the erasure unit number. The erasure unit number is subsequently nullified in the erasure-unit-number hold region when the transferring step is complete.
Moreover, the write data is written in response to a first write request, which requests writing of the write data into the erasure-unit region of the memory. The non-changing data is copied in response to the first write request, and the non-changing data is erased from the erasure-unit region after the non-changing data is completely copied.
A second write data is then written into a write buffer in response to a second write request for requesting writing of the second write data, after the step of writing write data, whereby the write buffer comprises a third region of the non-volatile memory. The write data and non-changing data, in the erasure block buffer, are transferred into the erasure-unit region after second write data is written.
Furthermore, the status of the erasure unit number is determined by comparing the erasure-unit region, to which the write data is to be written, with the erasure-unit region, to which the second write data is to be written. In a case where a match is obtained, processing pertaining to the writing second data and processing pertaining to transferring the write data and non-changing data are performed.
In a further embodiment, a data storage method is provided, for rewriting data into a memory having a plurality of erasure-unit regions. Write data is written to a nonvolatile erasure block buffer. Non-changing data, which is written in predetermined units, is copied from the memory to the erasure block buffer. The non-changing data is then erased from the erasure-unit regions. Both of the non-changing data and the write data are then transferred from the erasure block buffer to the memory. First write data is written, during a first erasure block buffer write step, to the erasure block buffer, in respons
Kobayashi Saburo
Settsu Atsushi
Sugai Naoto
Birch, Stewart, Kolash & Birch LLP
Gossage Glenn
Mitsubishi Denki & Kabushiki Kaisha
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