Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-10-13
2004-04-20
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S113000, C711S118000, C711S149000, C711S150000, C710S039000, C710S055000
Reexamination Certificate
active
06725348
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to improved storage devices and in particular to an improved method and system for writing data to a storage device. Still more particularly, the present invention relates to an improved method and system for completing the data transfer portion of write commands queued for the storage device.
2. Description of the Related Art
As the performance of microprocessor and semiconductor memory technology increases, there is a need for improved data storage devices with comparable performance enhancements. The typical data storage device comprises an interface to a host computer system, through which it receives commands and through which data is transferred between the host computer system and the storage device. It further comprises physical storage media, such as magnetic or optical platters (disks), on which data is stored. In enhancing the performance of data storage devices, there is a need for improved interaction with system processors and memory devices. The performance of data storage devices is critical in present computer systems, as programs and data are stored on these devices, and must be loaded before the computer performs any operations. In addition, data storage devices are often used as the lowest level of storage in a memory hierarchy consisting of cache memories, main Random Access Memory (RAM) and finally data storage devices (drives). “Page swaps” are made to the storage devices, allowing more efficient use of RAM by writing pages of RAM that have not been recently used to the storage device, freeing the physical memory page for use by the system until it is needed again. When the page is needed again, the system will retrieve it from the storage device, placing it back in physical RAM. While this improves overall system performance, it places a heavy load on data storage devices that are used for swap area.
Data storage devices currently in use in personal computer products and network arrays today are intelligent drives, in that they have integrated controllers and cache memory within the drive electronics. The interfaces in use today include Small Computer System Interface (SCSI), Integrated Drive Electronics (IDE), Enhanced Small Device Interface (ESDI) and “Firewire” (IEEE 1394). Each of these interface types includes a command protocol, wherein read, write and positioning commands can be issued to the drive in order to obtain data from, or write data to the physical storage media.
There are different methods for transferring data between the drive controller and a computer system. Direct Memory Access (DMA) is a method wherein a controller on a bus, typically one dedicated to performing DMA transfers, is supplied. A transfer is programmed into the DMA controller, and the controller moves data between a device and memory. This technique has the advantage of offloading the task of moving data from the processor, at a cost of having a DMA controller contending for the bus with the main processor, as well as the additional cost of having the controller in the system.
Another widely used transfer technique is programmed input/output (PIO). PIO simply means that a main processor in the computer performs the data transfer via memory and or port manipulation instructions. The advantage to this technique is that there is no bus contention, the disadvantage that the processor is occupied with transferring the data and therefore cannot perform other tasks while the transfer is completing.
Thus, a data storage device can be a bottleneck in computer system performance. A computer, for example, can issue a series of commands via a SCSI interface to a disk drive, but the disk drive can only process one data transfer to a physical disk at a time. The transfer controller within the drive is typically busy performing these transfers from the host computer system to the disk drive write electronics, while a write command is being completed. Usually, when a write command is received from the host, a seek operation is performed to move the head to the proper position to write the next data block. But, at times the seek operation completes before the host has started the transfer of data to the drive, causing the write to miss. The write must then be retried, at a cost of system performance. This happens frequently when large amounts of data are being written in contiguous clusters.
A disadvantage of present storage devices is that while write commands are being processed, other operations are suspended. So, if a write miss occurs, all of the operations are delayed. In general, all commands issued after a write command are delayed, pending completion of the write transfer to the physical storage media.
It would therefore be desirable to devise a method that will improve the performance of a storage device by reducing or eliminating missed writes. In addition, it would be desirable to devise a storage device with improved performance by decreasing the probability that host data is not ready when the write seek has completed. It would further be desirable to devise a method and data storage device that will allow further processing of commands while writes to the physical storage media are still pending.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved data storage device for a computer system.
It is another one object of the present invention to provide a method to improve the throughput of a direct access storage device (DASD).
The foregoing objects are achieved in a method for improving performance of a direct access storage device and a direct access storage device wherein the data transfer portion of write commands is completed before the transfer to the storage media is commenced. A process in the idle loop of the device's controller examines the command queue and sets up a DMA controller to perform the data transfer portion of write commands from an interface to a dual-port cache, while transfer of data to the physical disk is still pending or occurring from a prior command. Upon completion of the prior command, an interrupt is generated and in response to the interrupt, the interrupt is serviced, and if any data is ready for transfer from the cache to the storage media, a second DMA controller is set up to complete the transfer.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4394732 (1983-07-01), Swenson
patent: 4800483 (1989-01-01), Yamamoto et al.
patent: 4870565 (1989-09-01), Yamamoto et al.
patent: 5125084 (1992-06-01), Begun et al.
patent: 5179684 (1993-01-01), Tohchi et al.
patent: 5345561 (1994-09-01), Kato
patent: 5701516 (1997-12-01), Cheng et al.
patent: 6055583 (2000-04-01), Robbins
patent: 0510245 (1992-10-01), None
Hennessy, et al. Computer Organiation and Design: The Hardware/Software Interface, 2nded. 1997. Morgan Kaufmann Publishers, Inc., pp. 436-449.
Marier Louise Ann
Morger Brian Lee
Wiederholt Christopher David
Bracewell & Patterson LLP
International Business Machines - Corporation
Peikari B. James
Truelson Roy W.
LandOfFree
Data storage device and method for reducing write misses by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data storage device and method for reducing write misses by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data storage device and method for reducing write misses by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3192126