Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate
2005-12-22
2008-11-11
Lane, Jane A (Department: 2185)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
C711S100000, C711S109000, C711S113000, C710S052000, C710S053000, C710S056000
Reexamination Certificate
active
07451261
ABSTRACT:
Embodiments of the invention improve the cache hit ratio of read data. A hard disk drive (HDD) according to an embodiment of the present invention determines whether the read buffer should be used in its entirety or the partial continuous space should be used to read read-data from the magnetic disk. When the HDD determines use of the partial continuous space, the HDD specifies the sub-buffer which is a continuous space wherein the leading-end position and the trailing-end position are coupled to each other, and executes data writing to the sub-buffer in parallel with data reading from the sub-buffer and transmission thereof to the host. The sub-buffer capacity coincides with the data length of the back data.
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patent: 6782461 (2004-08-01), Lam
patent: 7085087 (2006-08-01), Fukuhisa et al.
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patent: 07-093888 (1995-04-01), None
patent: 2003-122631 (2003-04-01), None
Kanamaru Atsushi
Kobayashi Hiromi
Saito Takahiro
Yamaguchi Takayuki
Duncan Patrick
Hitachi Global Storage Technologies - Netherlands B.V.
Lane Jane A
Townsend and Townsend / and Crew LLP
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