Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2008-12-22
2011-12-06
Rutz, Jared (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S159000, C711S166000, C711S210000
Reexamination Certificate
active
08074048
ABSTRACT:
A storage device includes a memory for storing data in a plurality of logical volumes; a controlling unit for controlling an access to data in accordance with a process comprising the steps of: generating mapping information indicative of a correspondence between logical volume information and recognition information; generating a pseudo logical volume and pseudo logical volume information associated with the pseudo logical volume, the pseudo logical volume being another of the logical volumes; and upon receipt of a command for canceling an assignment of one of the logical volumes to the corresponding recognition information, modifying the mapping information so that recognition information that has been indicative of said one of the logical volumes becomes indicative of the pseudo logical volume information associated with the pseudo logical volume.
REFERENCES:
patent: 2004/0054866 (2004-03-01), Blumenau et al.
patent: 2004/0260870 (2004-12-01), Factor et al.
patent: 2005/0172005 (2005-08-01), Goodwin
patent: 2008/0133865 (2008-06-01), Qi et al.
patent: 2008/0209158 (2008-08-01), Asano et al.
patent: 2001-249769 (2001-09-01), None
patent: 2007-102512 (2007-04-01), None
Bertram Ryan
Fujitsu Limited
Rutz Jared
Staas & Halsey , LLP
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