Data storage circuit using shared bit line and method therefor

Static information storage and retrieval – Systems using particular element – Capacitors

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Details

365 63, 365174, 365190, G11C 700

Patent

active

060727136

ABSTRACT:
An integrated circuit includes a memory array implemented with as few as two transistors, and four access lines per cell. The array includes row lines and bit lines, with the internally-arranged bit lines shared by two adjacent cells. According to one embodiment, each memory cell includes a first transistor-based circuit in a first cell that is arranged to store information received over a corresponding one of the bit lines, and a second transistor-based circuit in a second cell that is arranged to output information over the same corresponding bit line.

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