Data signal distribution circuit for synchronous memory device

Static information storage and retrieval – Addressing – Sync/clocking

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365193, 365194, G11C 800

Patent

active

056216980

ABSTRACT:
A data signal distribution circuit for a synchronous memory device comprising a data generation source for generating successive data signals in response to an external clock signal. The data signal distribution circuit comprises at least two control switches for switching the data signals from the data generation source to at least two peripheral circuits, a strobe signal generator for delaying the external clock signal by a propagation delay time of the data generation source and generating a strobe signal in response to the delayed external clock signal, and an internal address generator for generating an internal address signal in response to the strobe signal from the strobe signal generator and supplying the generated internal address signal to the control switches. The strobe signal has a predetermined logic level for a predetermined duration beginning with a pulse edge of the delayed external clock signal. The internal address signal has at least two bits, only one of which has the predetermined logic level.

REFERENCES:
patent: 5107465 (1992-04-01), Fung et al.
patent: 5414672 (1995-05-01), Ozeki et al.
patent: 5475646 (1995-12-01), Ogihara

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