Data sequencing and registering in a four bit pre-fetch SDRAM

Details Data sequencing and registering in a four bit pre-fetch SDRAM Data sequencing and registering in a four bit pre-fetch SDRAM

1997-07-11

1999-09-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Sipo/piso

365 63, 365 72, 36518902, 36523003, G11C 700

Patent

active

059532785

ABSTRACT:
A memory device uses data circuitry to connect data lines extending from memory cell arrays to data signal bond pads. The data circuitry connect four data lines to one data signal bond pad. The data circuitry include data sequencer circuits, parallel data in circuits and serial data register circuits. The parallel data in circuits operate to write data to the memory device. The serial data register circuits operate to read and write data. The data sequencer circuits operate to connect the data lines to the bond pad in a selected order in a four bit pre-fetch architecture for normal and interleaved data modes.

REFERENCES:
patent: 5517442 (1996-05-01), Kirihata et al.
patent: 5596541 (1997-01-01), Toda
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5691949 (1997-11-01), Hively et al.
patent: 5802005 (1998-09-01), Nakamura et al.
patent: 5822257 (1998-10-01), Ogawa

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