Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1999-07-15
2002-11-12
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S033000, C710S051000, C712S032000, C712S226000, C712S300000, C717S152000, C717S152000
Reexamination Certificate
active
06480913
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to computer systems and more particularly, to data sequencing within computer systems.
BACKGROUND OF THE INVENTION
Data in a computer system may be organized in different formats. Three methods commonly used are little endian, big endian, and bitmap formats. Little and big endian formats vary the significance of bytes in multibyte words. In big endian systems, for example, the leftmost bytes are most significant. In little endian systems, however, the rightmost bytes are most significant. Computer systems can be configured to handle either or both types of endian data formats.
A graphical image may be represented in computer memory by the well known bitmap format. More particularly, in systems that utilize bitmap formats, data streams of ones and zeros may be produced by means of a simple sequencer. The ones and zeros in the stream may represent the state of pixels, for example, on a computer monitor. A “1” value, for example, may represent a lit pixel, while a “0” value may represent an unlit pixel. The combination of lit and unlit pixels produce a text character on a computer monitor.
Systems utilizing either or both the big and little endian formats, however, require special handling to reorder the data into a format that is understandable to a downstream device such as, for example, a computer monitor or a printer.
FIG. 1
shows a prior art system for sequencing received 32-bit data or words (from a microprocessor, for example) into a readable format for the downstream device. Each 32-bit word (input word
10
) received by the system has four bytes; namely B
0
, B
1
, B
2
, and B
3
. In this system, four possible types of word formats (represented by word codes “00”, “01”, “10” and “11”) may be converted into a readable bit stream
17
. Specifically, the four disclosed bytes (B
0
, B
1
, B
2
, and B
3
) are positioned at different locations within each word defined by each of the four word formats. Upon receipt of one of the four word formats, the system of
FIG. 1
first reorders the bytes to the order defined by the word format identified by the word code “00” (i.e., little endian format). This reordering is performed by passing the four bytes through a 32-bit wide 4-to-1 multiplexer
11
. The 4-to-1 multiplexer
11
has four one-byte wide inputs for receiving each of the four bytes of the input word
10
. The multiplexer has a two-bit select input
15
for receiving the word code. The 4-to-1 multiplexer
11
is configured to reorder the received word based upon the word code received by the select input
15
. For example, for the word code “00” (i.e., little endian format), the bytes of the input word
10
will be reordered to B
0
, B
1
, B
2
, B
3
.
After the input word
10
is reordered, the system utilizes a sequencer
18
to produce a bit stream
17
that has the bits arranged in a preselected order for use by the downstream hardware device. To that end, the sequencer
18
includes a 5-bit counter
12
and a 32-to-1 multiplexer
13
. In the embodiment shown, the counter
12
counts from 0 to 31 which, when such data is received by the 32-to-1 multiplexer
13
, causes the 32-to-1 multiplexer
13
to read first from the first multiplexer input line (i.e., the least significant bit), then the second multiplexer input line, etc. until the final (thirty-second) multiplexer input line (i.e., the most significant bit) is read. A drawback to the sequencer
18
shown in
FIG. 1
, however, is the large amount of circuit area and delay time taken up by the 32-bit 4-to-1 multiplexer
11
.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a system converts an input data stream in a first format (identified by a first stream code having at least two bits) into an output data stream in a second format. To that end, the system includes, among other things, a data sequencer for sequencing the input data stream. The sequencer includes a select input having a first number of selection input locations, a data input for receiving the input data stream, and output for transmitting the output data stream. The system further includes a counter having the first number of selection outputs, and first and second logic elements that are each connected to different selection input locations of the data sequencer. More particularly, the first logic element has an output coupled to a first of the selection input locations, and a two-bit input for receiving at least two bits. One bit input of the two-bit input receives a first bit of the stream code, while a second bit input of the two-bit input is coupled to one of the selection outputs of the counter. In a similar manner, the second logic element has an output coupled to a second of the selection input locations, and a two-bit input for receiving at least two bits. One bit input of the two-bit input receives a second bit of the stream code, while a second bit input of the two-bit input is coupled to a second of the selection outputs of the counter. In preferred embodiments, the first and second logic elements control the data sequencer to convert the input data stream into the output data stream in the second format.
In preferred embodiments, the first data stream is received from a first computer element such as, for example, a computer microprocessor, while the second data stream is directed to another computer element such as, for example, a computer monitor or a printer. Moreover, the logic elements preferably are exclusive-or (“XOR”) gates, or other devices producing equivalent output. In some embodiments, the first and second data formats are endian formats.
In other aspects of the invention, the second bit input of the first logic element is coupled to a first selection output of the counter, and the second bit input of the second logic element is coupled to a second selection output of the counter. In preferred embodiments, the first selection output outputs a more significant bit than that outputted by the second selection output. In other embodiments, the counter counts consecutively ascending numbers between zero and thirty-one. In a preferred embodiment, the counter is a modulo counter. In yet another embodiment, the system further includes a third logic element which has as output coupled to a third of the selection input locations, and a two-bit input for receiving at least two bits. One bit input of the two-bit input receives a third bit of the stream code, while a second bit input of the two-bit input is coupled to one of the selection outputs of the counter.
REFERENCES:
patent: 4434437 (1984-02-01), Strolle et al.
patent: 4615013 (1986-09-01), Yan et al.
patent: 4646232 (1987-02-01), Chang et al.
patent: 4908780 (1990-03-01), Priem et al.
patent: 4918626 (1990-04-01), Watkins et al.
patent: 4991122 (1991-02-01), Sanders
patent: 5107415 (1992-04-01), Sato et al.
patent: 5123085 (1992-06-01), Wells et al.
patent: 5200749 (1993-04-01), Crosby et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5287438 (1994-02-01), Kelleher
patent: 5293480 (1994-03-01), Miller et al.
patent: 5313551 (1994-05-01), Labrousse et al.
patent: 5319759 (1994-06-01), Chan
patent: 5363475 (1994-11-01), Baker et al.
patent: 5371840 (1994-12-01), Fischer et al.
patent: 5394524 (1995-02-01), DiNicola et al.
patent: 5398328 (1995-03-01), Weber et al.
patent: 5446479 (1995-08-01), Thompson et al.
patent: 5485559 (1996-01-01), Sakaibara et al.
patent: 5511165 (1996-04-01), Brady et al.
patent: 5519823 (1996-05-01), Barkans
patent: 5544294 (1996-08-01), Cho et al.
patent: 5555359 (1996-09-01), Choi et al.
patent: 5557734 (1996-09-01), Wilson
patent: 5561749 (1996-10-01), Schroeder
patent: 5572713 (1996-11-01), Weber et al.
patent: 5572813 (1996-11-01), Mastuoka
patent: 5631693 (1997-05-01), Wunderlich et al.
patent: 5664114 (1997-09-01), Krech, Jr. et al.
patent: 5666520 (1997-09-01), Fujita et al.
patent: 5684939 (1997-11-01), Foran et al.
patent: 5701365 (1997-12-01), Harrington et al.
patent: 5706481 (1998-01-01), Hannah et al.
patent: 5721812 (1998-02-01), Mochizuki
3Dlabs Inc. Led.
Bockhop & Reich, LLP
Lee Thomas
Peyton Tammara
LandOfFree
Data sequencer with MUX select input for converting input... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data sequencer with MUX select input for converting input..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data sequencer with MUX select input for converting input... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2950091