Data sense circuit for dynamic random access memories

Details Data sense circuit for dynamic random access memories Data sense circuit for dynamic random access memories

1995-09-28

1996-10-01

Nelms, David C.

Static information storage and retrieval

Read/write circuit

36518902, 365201, 365203, 371 213, G11C 700, G11C 2900

Patent

active

055616305

ABSTRACT:
An improved data sense for a DRAM. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.

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S. Dhong, et al, "Fully-Divided Bit Line for Dynamic Random-Access Memory Sensing Circuitry" IBM Technical Disclosure Bulletin, V. 31, No. 7, pp. 266-272, Dec. 1988.

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