Data selecting memory device and selected data transfer device

Details Data selecting memory device and selected data transfer device Data selecting memory device and selected data transfer device

2000-06-15

2004-03-30

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S100000, C711S154000, C365S189050

Reexamination Certificate

active

06715028

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a selective data memory device and a selected data transfer device, and more specifically to a selective data memory device and a selected data transfer device of a large capacity, which can effectively access a data set whose key string matches.
BACKGROUND ART
With the recent advance in the capacity of semiconductor memory devices, the quantity of data processed by an information apparatus has been increased greatly. Under these circumstances, the data selection for finding out data which satisfy some conditions from a great amount of accumulated data has become more important.
On the other hand, in the ordinary memory device, as shown in
FIG. 20
, an address Add is allocated to a cell data CD in a one-to-one corresponding relationship. Therefore, when data are required to be selected, it is necessary to access all the addresses to read all the cell data and further to select some data from all the cell data. However, when the memory capacity increases, the times required for both memory access and data selection increase markedly according to the increased memory capacity.
To overcome the above-mentioned situation, a method of accessing data by reference to-data contents (referred to as key string data access, hereinafter) has been proposed. In this method, a part of a group of data stored in the memory device is determined as key string data; key string data are given for each memory access; and a group of data whose key string data matches the given key string data are accessed.
FIG. 21
shows a conceptual illustration explaining key string data access. For example, in the case of an 8-bit key string, the key string data KSD can be set to any one of 2
8
states. It is optional as to which data set DS corresponds to one key string data. For instance, it is possible to allow a data set DSO (enclosed by a solid line) or a data set DS
1
(enclosed by a dashed line) to correspond to the key string data. When a data set stored in correspondence to a key string data as described above is required to be read from the memory, the data set can be read by giving the key string data, without reading all the data stored in the memory device.
A dynamic memory of key string data access type, which is suitable for data selection in a large-capacity memory, is disclosed in U.S. Pat. No. 4,989,180 entitled “Dynamic Memory with Logic-in-Refresh.” According to the disclosure of this patent, the dynamic memory refresh and the data selection based upon the key string data are executed simultaneously. When a match of the key string data is detected, a specific bit of the detected data is written as a mark bit. Further, when data is read, this bit data is read by detecting the mark bit. If a plurality of matched data sets exist in a selected row, a priority circuit selects only one matched data and outputs the selected matched data. The second and beyond matched data are read by selecting the rows again to read the matched data set.
In the above-mentioned prior art memory device of key string data access type, the key string data access can be technically realized, but it is practically impossible to apply this prior art memory device to a large capacity memory device such as DRAM, for instance. In addition, when a plurality of data to be read exist in the same row, there exists a problem in that the data reading efficiency is degraded markedly.
SUMMARY OF THE INVENTION
With these problems in mind, therefore, it is the object of the present invention to provide a large capacity selective data memory device and a large capacity selected data transfer device for enabling the key string data access and for enabling a highly efficient access to a data set which matches the key string data.
To achieve the above-mentioned object, the present invention provides a selective data memory device which comprises: a memory cell array composed of a plurality of memory cells arranged into a matrix pattern and divided into a plurality of column blocks; and selected data transferring means for comparing externally inputted string data with data in each column, marking some of the column blocks according to the comparison results, and transferring and outputting data in the marked column blocks in sequence.
In the selective data memory device according to the present invention, the externally input string data are compared with the data in the respective column blocks, and some of the column blocks are marked according to the comparison results for data selection. Further in the succeeding step, data in the marked columns are transferred by the selected data transferring means. As a result, it is possible to realize key string data access and an effective access to a data set that matches the key string data.
Further, in the selective data memory device according to the present invention, it is possible to write specific data in the cell data string on the basis of an externally supplied data string so that only the written cell data string can be read. Further, in the selected data transfer device according to the present invention, it is possible to transfer the cell data string in which previously determined specific data have been written on the basis of an externally applied reiterative pulse drive signal.


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Katsutaka, Kimura, et al., “A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture,” IEEE Journal of Solid State Circuits, vol. 26, No. 11, pp. 1511-1518, Nov. 1991.

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