Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2002-05-06
2004-06-22
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S029000, C327S198000
Reexamination Certificate
active
06753701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input buffer, in particular, to a data-sampling strobe clock generator in the input buffer, which uses non-inverting/inverting strobe signals to determine the strobe points for comparing the data signal and reference voltage, thereby overcoming timing issues while the system is in the idle state and when changing from the idle state to the operating state.
2. Description of the Related Art
FIG. 1
(Prior Art) is a circuit diagram of a conventional input buffer. In prior design implementation of the input buffer, non-inverting/inverting strobe signals (STROB/STROB#) are sent to a differential comparator
10
which generates a data-sampling strobe signal (STB) in view of the crossing points of these two strobe signals. Since the non-inverting/inverting strobe signals (STROB/STROB#) have a T/2 phase difference, where T represents the period of these two strobe signals, adjacent rising/falling edges of the data-sampling strobe signal (STB) are spaced out T/2 apart. In addition, differential comparator
20
receives a data signal (DATA) and a reference voltage (VREF) and compares them based on the rising/falling edges of the data-sampling strobe signal (STB), for determining logic levels of the output signal (DOUT), such as “1” or “0.”
FIG. 2
(Prior Art) is a timing diagram illustrating the relationships between the data signal (DATA), the reference voltage (VREF) and the non-inverting/inverting strobe signal (STROB/STROB#) in the conventional input buffer. As shown in the figure, a crossing point T
1
occurs when the level of the non-inverting strobe signal (STROB) is going down and the level of the inverting strobe signal (STROB#) is going up. At this time, the level of the data signal (DATA) is higher than the reference voltage (VREF) and thus the output signal (DOUT) is set to be “1.” On the other hand, a crossing point T
2
occurs when the level of the non-inverting signal (STROB) is going up and the level of the inverting signal (STROB#) is going down. At this time, the level of the data signal (DATA) is lower than the reference voltage (VREF) and thus the output signal (DOUT) is set to be “0.”
In fact, for some current bus implementation, such as Intel Pentium 4 microprocessor, the non-inverting/inverting strobe signals (STROB/STROB#) will all stay at logic “1” when they are idle. However, the conventional scheme of keeping the non-inverting/inverting strobe signals (STROB/STROB#) at logic “1” during the idle period has the following drawbacks:
1. When the system initially switches from the idle state to the normal operating state, a skew problem may occur at the first crossing point of the non-inverting/inverting strobe signals (STROB/STROB#), which corresponds to the first data sampling operation.
FIG. 3
(Prior Art) is a timing diagram of the non-inverting/inverting strobe signals (STROB/STROB#) in the conventional input buffer, which include the part corresponding to the state switch of the system from the idle state to the normal operating state. As shown in the figure, in the beginning of the idle state, the non-inverting/inverting strobe signals (STROB/STROB#) stay at the logic high level. At the time point T
3
, the non-inverting strobe signal (STROB) begins to go down from the logic high level and the inverting strobe signal (STROB#) still remains unchanged. However, the differential comparator
10
is able to sense the voltage difference between the non-inverting/inverting strobe signals (STROB/STROB#) since the non-inverting/inverting strobe signals (STROB/STROB#) start to differentiate and thus the time point T
3
is set as a crossing point, which is earlier than the regular crossing point T
4
by a time period &Dgr;t. The time skew may cause reading errors of the initial data, especially for high-speed systems.
2. Since all of the strobe signals (STROB/STROB#) stay at the logic high level in the idle state, the state of the data-sampling strobe signal (STB) generated by the differential comparator
10
may become unknown. Therefore, any small noise between the non-inverting/inverting strobe signals (STROB/STROB#) may induce extra glitch and cause the system to fail.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data-sampling strobe signal generator and an input buffer using the same, which can suppress the instability of the data-sampling strobe signal (STB) in the idle state due to the effect of noise.
Another object of the present invention is to provide a data-sampling strobe signal generator and an input buffer using the same, which can eliminate the skew phenomenon of the initial crossing point when the system switches from the idle state to the normal operating state.
The present invention achieves the above-indicated objects by providing a data-sampling strobe signal generator for generating a data-sampling strobe signal according to non-inverting/inverting strobe signals. The data-sampling strobe signal comprises an intermediate signal generator, a comparison circuit and a first logic circuit. The intermediate signal generator compares the non-inverting strobe signal and the inverting strobe signal and generates an intermediate signal based on the comparison result. The comparison circuit compares a reference voltage with the non-inverting strobe signal and the inverting strobe signal, respectively, and outputs a control signal. The control signal is enabled when one of the non-inverted/inverting strobe signals is higher than the reference voltage and the other is lower than the reference voltage, and disabled when the non-inverting/inverting strobe signals are the same logical level. The first logic circuit receives the intermediate signal and the control signal and generates the data-sampling strobe signal from the intermediate signal when the control signal is enabled. In addition, the data-sampling strobe signal is a constant logic level when the control signal is disabled.
In addition, the present invention also provides an input buffer. The input buffer includes a data comparator for comparing the data signal with the reference voltage in view of the data-sampling strobe signal and a data-sampling strobe signal generator, which has the same circuit structure described above, for generating the data-sampling strobe signal.
REFERENCES:
patent: 6016066 (2000-01-01), Ilkbahar
patent: 6288577 (2001-09-01), Wong
Chang Daniel D.
Rabin & Berdo P.C.
Via Technologies Inc.
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