Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2003-08-15
2008-08-05
Fan, Chieh M. (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000, C375S371000
Reexamination Certificate
active
07409031
ABSTRACT:
A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 μm CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10−12.
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Hwang Moon-Sang
Jeong Deog-Kyoon
Lee Bong-Joon
Lee Sang-Hyun
Fan Chieh M.
Girard & Equitz LLP
Joseoh Jaison
Silicon Image Inc.
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