Data sampling and recover in a phase-locked loop (PLL)

Details Data sampling and recover in a phase-locked loop (PLL) Data sampling and recover in a phase-locked loop (PLL)

1997-11-14

2000-03-21

Vo, Don N.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327148, 327149, 327157, 327158, 331 12, 331 60, H03D 324

Patent

active

060410906

ABSTRACT:
A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising: a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Also, a PLL circuit for recovering a clock signal from incoming data, comprising: a clock generator for generating an odd number, n, of phase-shifted adjacent clock signals; a data sampler for sampling the incoming data; a first pair of outputs from the sampler, for use in a phase detector (along with a reference clock of the adjacent clock signals and the incoming data), capable of producing an adjustment output. Another characterization is a method for recovering data in a PLL comprising the steps of: generating n phase-shifted adjacent clock signals for sampling bits incoming to the PLL; wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Similarly, a third of the adjacent clock signals can be used to clock bits 2, 2+n, 2+2n, . . . , as well as a fourth and fifth of the adjacent clock signals.

REFERENCES:
patent: 4151485 (1979-04-01), LaFratta
patent: 4573173 (1986-02-01), Yoshida
patent: 4672639 (1987-06-01), Tanabe et al.
patent: 4970609 (1990-11-01), Cunningham
patent: 5161173 (1992-11-01), Nordby
patent: 5212601 (1993-05-01), Wilson
patent: 5230013 (1993-07-01), Hanke et al.
patent: 5301196 (1994-04-01), Ewen et al.
patent: 5341405 (1994-08-01), Mallard, Jr.
patent: 5367542 (1994-11-01), Guo
patent: 5399995 (1995-03-01), Kardontchik et al.
patent: 5408200 (1995-04-01), Buhler
patent: 5483558 (1996-01-01), Leon et al.
patent: 5521948 (1996-05-01), Takeuchi
patent: 5574756 (1996-11-01), Jeong
Very High Speed Continuous Sampling Using Matched Delays; Electronics Letters; S. M. Clements et al.; Mar. 17, 1994; vol. 30, No. 6, ISSN 0013-5194; pp. 463-465.
Designing On-Chip Clock Generators; Dao-Long Chen; Circuits & Devices; Jul. 1992; pp. 32-36.
Multi-Gigabit-Per-Second Silicon Bipolar IC's for Future Optical-Fiber Transmission Systems; Hans-Martin Rein; IEEE Journal of Solid-State Circuits; Jun. 1988; pp. 664-675.
Electronic Communication Techniques; Paul H. Young; FM Transmitter Circuits; pp. 343, 345, 721, 722-723.
Principles of CMOS VLSI Design A systems Perspective; Neil H.E. Weste; Kamran Eshraghian; CMOS Circuit & Logic Design; pp. 334-336 & pp. 685-689.

Affiliated with

Also associated with

Rating

Data sampling and recover in a phase-locked loop (PLL) does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data sampling and recover in a phase-locked loop (PLL), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data sampling and recover in a phase-locked loop (PLL) will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-736314