Data retention weak write circuit and method of using same

Details Data retention weak write circuit and method of using same Data retention weak write circuit and method of using same

1997-05-09

1998-11-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365154, 365156, 365200, G11C 700, G11C 1100

Patent

active

058354298

ABSTRACT:
A test circuit is provided for detection of data retention faults and cell stability faults of a memory array, such as a static random access memory (SRAM). The memory array test circuit comprises a weak write test circuit, a memory array address decoder, a microprocessor and display unit. During testing of the memory array, the weak test circuit controls the address decoder to decrease the voltage on the word lines so that it is less than the threshold voltage of the memory array transistors. The microprocessor then writes an inverted data to the memory array and then reads it. The read inverted data is sent to the display unit for comparison with a known template. By comparing the read inverted data to the template, defective memory cells can be identified.

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