Data retention test for static memory cell

Details Data retention test for static memory cell Data retention test for static memory cell

1997-09-26

1999-07-27

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365200, 36518901, G11C 700

Patent

active

059301856

ABSTRACT:
A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled, but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.

REFERENCES:
patent: 5276647 (1994-01-01), Matsui et al.
patent: 5422852 (1995-06-01), Houston et al.
patent: 5428574 (1995-06-01), Kuo et al.
patent: 5463585 (1995-10-01), Sanada
patent: 5500823 (1996-03-01), Martin et al.
patent: 5517448 (1996-05-01), Liu
patent: 5687178 (1997-11-01), Herr et al.
patent: 5754468 (1998-05-01), Hobson
Sharma, A., "Semiconductor Memories: Technology, Testing, and Reliability," IEEE Solid-State Circuits Council, IEEE Press, New York, NY, 1997, pp. 222-247.
Seevinck, E., et al., "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE Journal of Solid-State Circuits, vol. sc-22, No. 5, Oct. 1987, pp. 748-754.
Hall, E., et al., "A Structured Approach for Failure Analysis of a 256K BiCMOS SRAM," ISTFA International Symposium for Testing and Failure Analysis; Conference Proceedings; ASM Int., Materials Park, OH, Nov. 1989, pp. 167-176.

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