Data retention mode control circuit

Details Data retention mode control circuit Data retention mode control circuit

1992-12-02

1994-06-07

LaRoche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

365194, 365203, 365233, 307590, H03K 386, H03K 514

Patent

active

053192532

ABSTRACT:
A semiconductor memory device with data retention function to retain data is provided with a sense amplifier control signal generating circuit comprising a switching circuit controlled by a data retention mode detection signal so as to make the time interval between enabling of a word line and starting of an N- or P-type sense amplifier longer in data retention mode than in normal mode. Thus the inventive circuit generates a sense amplifier control signal whose delay time differs in the normal and data retention modes, so that the data retention mode is performed without influencing the operational speed, the charge sharing is sufficiently achieved in the data retention mode, and the direct current flowing is prevented.

REFERENCES:
patent: 5033026 (1991-07-01), Tsujimoto
patent: 5206830 (1993-04-01), Isobe et al.

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