Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-09-26
2006-09-26
Chase, Shelly (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07114115
ABSTRACT:
A data reproducing controller for operating a device for reproducing data at a high speed, which is recorded on a disc and includes an error correction code. A PI correction circuit performs an error correction process on a PI and causes a completion signal to go high whenever processing of 182 bytes of data is completed. A counter circuit sequentially increments a count value whenever the completion signal goes high. A determination circuit compares the count value with a predetermined set value and determines whether the data of which PI has undergone the error correction process is a PO row based on the comparison. The determination circuit causes a first control signal to go low when the data is a PO row. A descrambling circuit skips the data that is determined to be a PO row.
REFERENCES:
patent: 5051998 (1991-09-01), Murai et al.
patent: 6760878 (2004-07-01), Yashima
patent: 6772386 (2004-08-01), Iwata et al.
patent: 1998-043708 (1998-09-01), None
patent: 1999-0084682 (1999-12-01), None
Nagai Hiroki
Tomisawa Shin'ichiro
Chase Shelly
Fish & Richardson P.C.
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